1 /// @file xed-reg-enum.c
2
3 // This file was automatically generated.
4 // Do not edit this file.
5
6 #include <string.h>
7 #include <assert.h>
8 #include "xed-reg-enum.h"
9
10 typedef struct {
11 const char* name;
12 xed_reg_enum_t value;
13 } name_table_xed_reg_enum_t;
14 static const name_table_xed_reg_enum_t name_array_xed_reg_enum_t[] = {
15 {"INVALID", XED_REG_INVALID},
16 {"BNDCFGU", XED_REG_BNDCFGU},
17 {"BNDSTATUS", XED_REG_BNDSTATUS},
18 {"BND0", XED_REG_BND0},
19 {"BND1", XED_REG_BND1},
20 {"BND2", XED_REG_BND2},
21 {"BND3", XED_REG_BND3},
22 {"CR0", XED_REG_CR0},
23 {"CR1", XED_REG_CR1},
24 {"CR2", XED_REG_CR2},
25 {"CR3", XED_REG_CR3},
26 {"CR4", XED_REG_CR4},
27 {"CR5", XED_REG_CR5},
28 {"CR6", XED_REG_CR6},
29 {"CR7", XED_REG_CR7},
30 {"CR8", XED_REG_CR8},
31 {"CR9", XED_REG_CR9},
32 {"CR10", XED_REG_CR10},
33 {"CR11", XED_REG_CR11},
34 {"CR12", XED_REG_CR12},
35 {"CR13", XED_REG_CR13},
36 {"CR14", XED_REG_CR14},
37 {"CR15", XED_REG_CR15},
38 {"DR0", XED_REG_DR0},
39 {"DR1", XED_REG_DR1},
40 {"DR2", XED_REG_DR2},
41 {"DR3", XED_REG_DR3},
42 {"DR4", XED_REG_DR4},
43 {"DR5", XED_REG_DR5},
44 {"DR6", XED_REG_DR6},
45 {"DR7", XED_REG_DR7},
46 {"FLAGS", XED_REG_FLAGS},
47 {"EFLAGS", XED_REG_EFLAGS},
48 {"RFLAGS", XED_REG_RFLAGS},
49 {"AX", XED_REG_AX},
50 {"CX", XED_REG_CX},
51 {"DX", XED_REG_DX},
52 {"BX", XED_REG_BX},
53 {"SP", XED_REG_SP},
54 {"BP", XED_REG_BP},
55 {"SI", XED_REG_SI},
56 {"DI", XED_REG_DI},
57 {"R8W", XED_REG_R8W},
58 {"R9W", XED_REG_R9W},
59 {"R10W", XED_REG_R10W},
60 {"R11W", XED_REG_R11W},
61 {"R12W", XED_REG_R12W},
62 {"R13W", XED_REG_R13W},
63 {"R14W", XED_REG_R14W},
64 {"R15W", XED_REG_R15W},
65 {"EAX", XED_REG_EAX},
66 {"ECX", XED_REG_ECX},
67 {"EDX", XED_REG_EDX},
68 {"EBX", XED_REG_EBX},
69 {"ESP", XED_REG_ESP},
70 {"EBP", XED_REG_EBP},
71 {"ESI", XED_REG_ESI},
72 {"EDI", XED_REG_EDI},
73 {"R8D", XED_REG_R8D},
74 {"R9D", XED_REG_R9D},
75 {"R10D", XED_REG_R10D},
76 {"R11D", XED_REG_R11D},
77 {"R12D", XED_REG_R12D},
78 {"R13D", XED_REG_R13D},
79 {"R14D", XED_REG_R14D},
80 {"R15D", XED_REG_R15D},
81 {"RAX", XED_REG_RAX},
82 {"RCX", XED_REG_RCX},
83 {"RDX", XED_REG_RDX},
84 {"RBX", XED_REG_RBX},
85 {"RSP", XED_REG_RSP},
86 {"RBP", XED_REG_RBP},
87 {"RSI", XED_REG_RSI},
88 {"RDI", XED_REG_RDI},
89 {"R8", XED_REG_R8},
90 {"R9", XED_REG_R9},
91 {"R10", XED_REG_R10},
92 {"R11", XED_REG_R11},
93 {"R12", XED_REG_R12},
94 {"R13", XED_REG_R13},
95 {"R14", XED_REG_R14},
96 {"R15", XED_REG_R15},
97 {"AL", XED_REG_AL},
98 {"CL", XED_REG_CL},
99 {"DL", XED_REG_DL},
100 {"BL", XED_REG_BL},
101 {"SPL", XED_REG_SPL},
102 {"BPL", XED_REG_BPL},
103 {"SIL", XED_REG_SIL},
104 {"DIL", XED_REG_DIL},
105 {"R8B", XED_REG_R8B},
106 {"R9B", XED_REG_R9B},
107 {"R10B", XED_REG_R10B},
108 {"R11B", XED_REG_R11B},
109 {"R12B", XED_REG_R12B},
110 {"R13B", XED_REG_R13B},
111 {"R14B", XED_REG_R14B},
112 {"R15B", XED_REG_R15B},
113 {"AH", XED_REG_AH},
114 {"CH", XED_REG_CH},
115 {"DH", XED_REG_DH},
116 {"BH", XED_REG_BH},
117 {"ERROR", XED_REG_ERROR},
118 {"RIP", XED_REG_RIP},
119 {"EIP", XED_REG_EIP},
120 {"IP", XED_REG_IP},
121 {"K0", XED_REG_K0},
122 {"K1", XED_REG_K1},
123 {"K2", XED_REG_K2},
124 {"K3", XED_REG_K3},
125 {"K4", XED_REG_K4},
126 {"K5", XED_REG_K5},
127 {"K6", XED_REG_K6},
128 {"K7", XED_REG_K7},
129 {"MMX0", XED_REG_MMX0},
130 {"MMX1", XED_REG_MMX1},
131 {"MMX2", XED_REG_MMX2},
132 {"MMX3", XED_REG_MMX3},
133 {"MMX4", XED_REG_MMX4},
134 {"MMX5", XED_REG_MMX5},
135 {"MMX6", XED_REG_MMX6},
136 {"MMX7", XED_REG_MMX7},
137 {"SSP", XED_REG_SSP},
138 {"IA32_U_CET", XED_REG_IA32_U_CET},
139 {"MXCSR", XED_REG_MXCSR},
140 {"STACKPUSH", XED_REG_STACKPUSH},
141 {"STACKPOP", XED_REG_STACKPOP},
142 {"GDTR", XED_REG_GDTR},
143 {"LDTR", XED_REG_LDTR},
144 {"IDTR", XED_REG_IDTR},
145 {"TR", XED_REG_TR},
146 {"TSC", XED_REG_TSC},
147 {"TSCAUX", XED_REG_TSCAUX},
148 {"MSRS", XED_REG_MSRS},
149 {"FSBASE", XED_REG_FSBASE},
150 {"GSBASE", XED_REG_GSBASE},
151 {"X87CONTROL", XED_REG_X87CONTROL},
152 {"X87STATUS", XED_REG_X87STATUS},
153 {"X87TAG", XED_REG_X87TAG},
154 {"X87PUSH", XED_REG_X87PUSH},
155 {"X87POP", XED_REG_X87POP},
156 {"X87POP2", XED_REG_X87POP2},
157 {"X87OPCODE", XED_REG_X87OPCODE},
158 {"X87LASTCS", XED_REG_X87LASTCS},
159 {"X87LASTIP", XED_REG_X87LASTIP},
160 {"X87LASTDS", XED_REG_X87LASTDS},
161 {"X87LASTDP", XED_REG_X87LASTDP},
162 {"CS", XED_REG_CS},
163 {"DS", XED_REG_DS},
164 {"ES", XED_REG_ES},
165 {"SS", XED_REG_SS},
166 {"FS", XED_REG_FS},
167 {"GS", XED_REG_GS},
168 {"TMP0", XED_REG_TMP0},
169 {"TMP1", XED_REG_TMP1},
170 {"TMP2", XED_REG_TMP2},
171 {"TMP3", XED_REG_TMP3},
172 {"TMP4", XED_REG_TMP4},
173 {"TMP5", XED_REG_TMP5},
174 {"TMP6", XED_REG_TMP6},
175 {"TMP7", XED_REG_TMP7},
176 {"TMP8", XED_REG_TMP8},
177 {"TMP9", XED_REG_TMP9},
178 {"TMP10", XED_REG_TMP10},
179 {"TMP11", XED_REG_TMP11},
180 {"TMP12", XED_REG_TMP12},
181 {"TMP13", XED_REG_TMP13},
182 {"TMP14", XED_REG_TMP14},
183 {"TMP15", XED_REG_TMP15},
184 {"st(0)", XED_REG_ST0},
185 {"st(1)", XED_REG_ST1},
186 {"st(2)", XED_REG_ST2},
187 {"st(3)", XED_REG_ST3},
188 {"st(4)", XED_REG_ST4},
189 {"st(5)", XED_REG_ST5},
190 {"st(6)", XED_REG_ST6},
191 {"st(7)", XED_REG_ST7},
192 {"XCR0", XED_REG_XCR0},
193 {"XMM0", XED_REG_XMM0},
194 {"XMM1", XED_REG_XMM1},
195 {"XMM2", XED_REG_XMM2},
196 {"XMM3", XED_REG_XMM3},
197 {"XMM4", XED_REG_XMM4},
198 {"XMM5", XED_REG_XMM5},
199 {"XMM6", XED_REG_XMM6},
200 {"XMM7", XED_REG_XMM7},
201 {"XMM8", XED_REG_XMM8},
202 {"XMM9", XED_REG_XMM9},
203 {"XMM10", XED_REG_XMM10},
204 {"XMM11", XED_REG_XMM11},
205 {"XMM12", XED_REG_XMM12},
206 {"XMM13", XED_REG_XMM13},
207 {"XMM14", XED_REG_XMM14},
208 {"XMM15", XED_REG_XMM15},
209 {"XMM16", XED_REG_XMM16},
210 {"XMM17", XED_REG_XMM17},
211 {"XMM18", XED_REG_XMM18},
212 {"XMM19", XED_REG_XMM19},
213 {"XMM20", XED_REG_XMM20},
214 {"XMM21", XED_REG_XMM21},
215 {"XMM22", XED_REG_XMM22},
216 {"XMM23", XED_REG_XMM23},
217 {"XMM24", XED_REG_XMM24},
218 {"XMM25", XED_REG_XMM25},
219 {"XMM26", XED_REG_XMM26},
220 {"XMM27", XED_REG_XMM27},
221 {"XMM28", XED_REG_XMM28},
222 {"XMM29", XED_REG_XMM29},
223 {"XMM30", XED_REG_XMM30},
224 {"XMM31", XED_REG_XMM31},
225 {"YMM0", XED_REG_YMM0},
226 {"YMM1", XED_REG_YMM1},
227 {"YMM2", XED_REG_YMM2},
228 {"YMM3", XED_REG_YMM3},
229 {"YMM4", XED_REG_YMM4},
230 {"YMM5", XED_REG_YMM5},
231 {"YMM6", XED_REG_YMM6},
232 {"YMM7", XED_REG_YMM7},
233 {"YMM8", XED_REG_YMM8},
234 {"YMM9", XED_REG_YMM9},
235 {"YMM10", XED_REG_YMM10},
236 {"YMM11", XED_REG_YMM11},
237 {"YMM12", XED_REG_YMM12},
238 {"YMM13", XED_REG_YMM13},
239 {"YMM14", XED_REG_YMM14},
240 {"YMM15", XED_REG_YMM15},
241 {"YMM16", XED_REG_YMM16},
242 {"YMM17", XED_REG_YMM17},
243 {"YMM18", XED_REG_YMM18},
244 {"YMM19", XED_REG_YMM19},
245 {"YMM20", XED_REG_YMM20},
246 {"YMM21", XED_REG_YMM21},
247 {"YMM22", XED_REG_YMM22},
248 {"YMM23", XED_REG_YMM23},
249 {"YMM24", XED_REG_YMM24},
250 {"YMM25", XED_REG_YMM25},
251 {"YMM26", XED_REG_YMM26},
252 {"YMM27", XED_REG_YMM27},
253 {"YMM28", XED_REG_YMM28},
254 {"YMM29", XED_REG_YMM29},
255 {"YMM30", XED_REG_YMM30},
256 {"YMM31", XED_REG_YMM31},
257 {"ZMM0", XED_REG_ZMM0},
258 {"ZMM1", XED_REG_ZMM1},
259 {"ZMM2", XED_REG_ZMM2},
260 {"ZMM3", XED_REG_ZMM3},
261 {"ZMM4", XED_REG_ZMM4},
262 {"ZMM5", XED_REG_ZMM5},
263 {"ZMM6", XED_REG_ZMM6},
264 {"ZMM7", XED_REG_ZMM7},
265 {"ZMM8", XED_REG_ZMM8},
266 {"ZMM9", XED_REG_ZMM9},
267 {"ZMM10", XED_REG_ZMM10},
268 {"ZMM11", XED_REG_ZMM11},
269 {"ZMM12", XED_REG_ZMM12},
270 {"ZMM13", XED_REG_ZMM13},
271 {"ZMM14", XED_REG_ZMM14},
272 {"ZMM15", XED_REG_ZMM15},
273 {"ZMM16", XED_REG_ZMM16},
274 {"ZMM17", XED_REG_ZMM17},
275 {"ZMM18", XED_REG_ZMM18},
276 {"ZMM19", XED_REG_ZMM19},
277 {"ZMM20", XED_REG_ZMM20},
278 {"ZMM21", XED_REG_ZMM21},
279 {"ZMM22", XED_REG_ZMM22},
280 {"ZMM23", XED_REG_ZMM23},
281 {"ZMM24", XED_REG_ZMM24},
282 {"ZMM25", XED_REG_ZMM25},
283 {"ZMM26", XED_REG_ZMM26},
284 {"ZMM27", XED_REG_ZMM27},
285 {"ZMM28", XED_REG_ZMM28},
286 {"ZMM29", XED_REG_ZMM29},
287 {"ZMM30", XED_REG_ZMM30},
288 {"ZMM31", XED_REG_ZMM31},
289 {"LAST", XED_REG_LAST},
290 {0, XED_REG_LAST},
291 };
292 static const name_table_xed_reg_enum_t dup_name_array_xed_reg_enum_t[] = {
293 {"BNDCFG_FIRST", XED_REG_BNDCFG_FIRST},
294 {"BNDCFG_LAST", XED_REG_BNDCFG_LAST},
295 {"BNDSTAT_FIRST", XED_REG_BNDSTAT_FIRST},
296 {"BNDSTAT_LAST", XED_REG_BNDSTAT_LAST},
297 {"BOUND_FIRST", XED_REG_BOUND_FIRST},
298 {"BOUND_LAST", XED_REG_BOUND_LAST},
299 {"CR_FIRST", XED_REG_CR_FIRST},
300 {"CR_LAST", XED_REG_CR_LAST},
301 {"DR_FIRST", XED_REG_DR_FIRST},
302 {"DR_LAST", XED_REG_DR_LAST},
303 {"FLAGS_FIRST", XED_REG_FLAGS_FIRST},
304 {"FLAGS_LAST", XED_REG_FLAGS_LAST},
305 {"GPR16_FIRST", XED_REG_GPR16_FIRST},
306 {"GPR16_LAST", XED_REG_GPR16_LAST},
307 {"GPR32_FIRST", XED_REG_GPR32_FIRST},
308 {"GPR32_LAST", XED_REG_GPR32_LAST},
309 {"GPR64_FIRST", XED_REG_GPR64_FIRST},
310 {"GPR64_LAST", XED_REG_GPR64_LAST},
311 {"GPR8_FIRST", XED_REG_GPR8_FIRST},
312 {"GPR8_LAST", XED_REG_GPR8_LAST},
313 {"GPR8h_FIRST", XED_REG_GPR8h_FIRST},
314 {"GPR8h_LAST", XED_REG_GPR8h_LAST},
315 {"INVALID_FIRST", XED_REG_INVALID_FIRST},
316 {"INVALID_LAST", XED_REG_INVALID_LAST},
317 {"IP_FIRST", XED_REG_IP_FIRST},
318 {"IP_LAST", XED_REG_IP_LAST},
319 {"MASK_FIRST", XED_REG_MASK_FIRST},
320 {"MASK_LAST", XED_REG_MASK_LAST},
321 {"MMX_FIRST", XED_REG_MMX_FIRST},
322 {"MMX_LAST", XED_REG_MMX_LAST},
323 {"MSR_FIRST", XED_REG_MSR_FIRST},
324 {"MSR_LAST", XED_REG_MSR_LAST},
325 {"MXCSR_FIRST", XED_REG_MXCSR_FIRST},
326 {"MXCSR_LAST", XED_REG_MXCSR_LAST},
327 {"PSEUDO_FIRST", XED_REG_PSEUDO_FIRST},
328 {"PSEUDO_LAST", XED_REG_PSEUDO_LAST},
329 {"PSEUDOX87_FIRST", XED_REG_PSEUDOX87_FIRST},
330 {"PSEUDOX87_LAST", XED_REG_PSEUDOX87_LAST},
331 {"SR_FIRST", XED_REG_SR_FIRST},
332 {"SR_LAST", XED_REG_SR_LAST},
333 {"TMP_FIRST", XED_REG_TMP_FIRST},
334 {"TMP_LAST", XED_REG_TMP_LAST},
335 {"X87_FIRST", XED_REG_X87_FIRST},
336 {"X87_LAST", XED_REG_X87_LAST},
337 {"XCR_FIRST", XED_REG_XCR_FIRST},
338 {"XCR_LAST", XED_REG_XCR_LAST},
339 {"XMM_FIRST", XED_REG_XMM_FIRST},
340 {"XMM_LAST", XED_REG_XMM_LAST},
341 {"YMM_FIRST", XED_REG_YMM_FIRST},
342 {"YMM_LAST", XED_REG_YMM_LAST},
343 {"ZMM_FIRST", XED_REG_ZMM_FIRST},
344 {"ZMM_LAST", XED_REG_ZMM_LAST},
345 {0, XED_REG_LAST},
346 };
347
348
str2xed_reg_enum_t(const char * s)349 xed_reg_enum_t str2xed_reg_enum_t(const char* s)
350 {
351 const name_table_xed_reg_enum_t* p = name_array_xed_reg_enum_t;
352 while( p->name ) {
353 if (strcmp(p->name,s) == 0) {
354 return p->value;
355 }
356 p++;
357 }
358
359
360 {
361 const name_table_xed_reg_enum_t* q = dup_name_array_xed_reg_enum_t;
362 while( q->name ) {
363 if (strcmp(q->name,s) == 0) {
364 return q->value;
365 }
366 q++;
367 }
368 }
369
370
371 return XED_REG_INVALID;
372 }
373
374
xed_reg_enum_t2str(const xed_reg_enum_t p)375 const char* xed_reg_enum_t2str(const xed_reg_enum_t p)
376 {
377 xed_reg_enum_t type_idx = p;
378 if ( p > XED_REG_LAST) type_idx = XED_REG_LAST;
379 return name_array_xed_reg_enum_t[type_idx].name;
380 }
381
xed_reg_enum_t_last(void)382 xed_reg_enum_t xed_reg_enum_t_last(void) {
383 return XED_REG_LAST;
384 }
385
386 /*
387
388 Here is a skeleton switch statement embedded in a comment
389
390
391 switch(p) {
392 case XED_REG_INVALID:
393 case XED_REG_BNDCFGU:
394 case XED_REG_BNDSTATUS:
395 case XED_REG_BND0:
396 case XED_REG_BND1:
397 case XED_REG_BND2:
398 case XED_REG_BND3:
399 case XED_REG_CR0:
400 case XED_REG_CR1:
401 case XED_REG_CR2:
402 case XED_REG_CR3:
403 case XED_REG_CR4:
404 case XED_REG_CR5:
405 case XED_REG_CR6:
406 case XED_REG_CR7:
407 case XED_REG_CR8:
408 case XED_REG_CR9:
409 case XED_REG_CR10:
410 case XED_REG_CR11:
411 case XED_REG_CR12:
412 case XED_REG_CR13:
413 case XED_REG_CR14:
414 case XED_REG_CR15:
415 case XED_REG_DR0:
416 case XED_REG_DR1:
417 case XED_REG_DR2:
418 case XED_REG_DR3:
419 case XED_REG_DR4:
420 case XED_REG_DR5:
421 case XED_REG_DR6:
422 case XED_REG_DR7:
423 case XED_REG_FLAGS:
424 case XED_REG_EFLAGS:
425 case XED_REG_RFLAGS:
426 case XED_REG_AX:
427 case XED_REG_CX:
428 case XED_REG_DX:
429 case XED_REG_BX:
430 case XED_REG_SP:
431 case XED_REG_BP:
432 case XED_REG_SI:
433 case XED_REG_DI:
434 case XED_REG_R8W:
435 case XED_REG_R9W:
436 case XED_REG_R10W:
437 case XED_REG_R11W:
438 case XED_REG_R12W:
439 case XED_REG_R13W:
440 case XED_REG_R14W:
441 case XED_REG_R15W:
442 case XED_REG_EAX:
443 case XED_REG_ECX:
444 case XED_REG_EDX:
445 case XED_REG_EBX:
446 case XED_REG_ESP:
447 case XED_REG_EBP:
448 case XED_REG_ESI:
449 case XED_REG_EDI:
450 case XED_REG_R8D:
451 case XED_REG_R9D:
452 case XED_REG_R10D:
453 case XED_REG_R11D:
454 case XED_REG_R12D:
455 case XED_REG_R13D:
456 case XED_REG_R14D:
457 case XED_REG_R15D:
458 case XED_REG_RAX:
459 case XED_REG_RCX:
460 case XED_REG_RDX:
461 case XED_REG_RBX:
462 case XED_REG_RSP:
463 case XED_REG_RBP:
464 case XED_REG_RSI:
465 case XED_REG_RDI:
466 case XED_REG_R8:
467 case XED_REG_R9:
468 case XED_REG_R10:
469 case XED_REG_R11:
470 case XED_REG_R12:
471 case XED_REG_R13:
472 case XED_REG_R14:
473 case XED_REG_R15:
474 case XED_REG_AL:
475 case XED_REG_CL:
476 case XED_REG_DL:
477 case XED_REG_BL:
478 case XED_REG_SPL:
479 case XED_REG_BPL:
480 case XED_REG_SIL:
481 case XED_REG_DIL:
482 case XED_REG_R8B:
483 case XED_REG_R9B:
484 case XED_REG_R10B:
485 case XED_REG_R11B:
486 case XED_REG_R12B:
487 case XED_REG_R13B:
488 case XED_REG_R14B:
489 case XED_REG_R15B:
490 case XED_REG_AH:
491 case XED_REG_CH:
492 case XED_REG_DH:
493 case XED_REG_BH:
494 case XED_REG_ERROR:
495 case XED_REG_RIP:
496 case XED_REG_EIP:
497 case XED_REG_IP:
498 case XED_REG_K0:
499 case XED_REG_K1:
500 case XED_REG_K2:
501 case XED_REG_K3:
502 case XED_REG_K4:
503 case XED_REG_K5:
504 case XED_REG_K6:
505 case XED_REG_K7:
506 case XED_REG_MMX0:
507 case XED_REG_MMX1:
508 case XED_REG_MMX2:
509 case XED_REG_MMX3:
510 case XED_REG_MMX4:
511 case XED_REG_MMX5:
512 case XED_REG_MMX6:
513 case XED_REG_MMX7:
514 case XED_REG_SSP:
515 case XED_REG_IA32_U_CET:
516 case XED_REG_MXCSR:
517 case XED_REG_STACKPUSH:
518 case XED_REG_STACKPOP:
519 case XED_REG_GDTR:
520 case XED_REG_LDTR:
521 case XED_REG_IDTR:
522 case XED_REG_TR:
523 case XED_REG_TSC:
524 case XED_REG_TSCAUX:
525 case XED_REG_MSRS:
526 case XED_REG_FSBASE:
527 case XED_REG_GSBASE:
528 case XED_REG_X87CONTROL:
529 case XED_REG_X87STATUS:
530 case XED_REG_X87TAG:
531 case XED_REG_X87PUSH:
532 case XED_REG_X87POP:
533 case XED_REG_X87POP2:
534 case XED_REG_X87OPCODE:
535 case XED_REG_X87LASTCS:
536 case XED_REG_X87LASTIP:
537 case XED_REG_X87LASTDS:
538 case XED_REG_X87LASTDP:
539 case XED_REG_CS:
540 case XED_REG_DS:
541 case XED_REG_ES:
542 case XED_REG_SS:
543 case XED_REG_FS:
544 case XED_REG_GS:
545 case XED_REG_TMP0:
546 case XED_REG_TMP1:
547 case XED_REG_TMP2:
548 case XED_REG_TMP3:
549 case XED_REG_TMP4:
550 case XED_REG_TMP5:
551 case XED_REG_TMP6:
552 case XED_REG_TMP7:
553 case XED_REG_TMP8:
554 case XED_REG_TMP9:
555 case XED_REG_TMP10:
556 case XED_REG_TMP11:
557 case XED_REG_TMP12:
558 case XED_REG_TMP13:
559 case XED_REG_TMP14:
560 case XED_REG_TMP15:
561 case XED_REG_ST0:
562 case XED_REG_ST1:
563 case XED_REG_ST2:
564 case XED_REG_ST3:
565 case XED_REG_ST4:
566 case XED_REG_ST5:
567 case XED_REG_ST6:
568 case XED_REG_ST7:
569 case XED_REG_XCR0:
570 case XED_REG_XMM0:
571 case XED_REG_XMM1:
572 case XED_REG_XMM2:
573 case XED_REG_XMM3:
574 case XED_REG_XMM4:
575 case XED_REG_XMM5:
576 case XED_REG_XMM6:
577 case XED_REG_XMM7:
578 case XED_REG_XMM8:
579 case XED_REG_XMM9:
580 case XED_REG_XMM10:
581 case XED_REG_XMM11:
582 case XED_REG_XMM12:
583 case XED_REG_XMM13:
584 case XED_REG_XMM14:
585 case XED_REG_XMM15:
586 case XED_REG_XMM16:
587 case XED_REG_XMM17:
588 case XED_REG_XMM18:
589 case XED_REG_XMM19:
590 case XED_REG_XMM20:
591 case XED_REG_XMM21:
592 case XED_REG_XMM22:
593 case XED_REG_XMM23:
594 case XED_REG_XMM24:
595 case XED_REG_XMM25:
596 case XED_REG_XMM26:
597 case XED_REG_XMM27:
598 case XED_REG_XMM28:
599 case XED_REG_XMM29:
600 case XED_REG_XMM30:
601 case XED_REG_XMM31:
602 case XED_REG_YMM0:
603 case XED_REG_YMM1:
604 case XED_REG_YMM2:
605 case XED_REG_YMM3:
606 case XED_REG_YMM4:
607 case XED_REG_YMM5:
608 case XED_REG_YMM6:
609 case XED_REG_YMM7:
610 case XED_REG_YMM8:
611 case XED_REG_YMM9:
612 case XED_REG_YMM10:
613 case XED_REG_YMM11:
614 case XED_REG_YMM12:
615 case XED_REG_YMM13:
616 case XED_REG_YMM14:
617 case XED_REG_YMM15:
618 case XED_REG_YMM16:
619 case XED_REG_YMM17:
620 case XED_REG_YMM18:
621 case XED_REG_YMM19:
622 case XED_REG_YMM20:
623 case XED_REG_YMM21:
624 case XED_REG_YMM22:
625 case XED_REG_YMM23:
626 case XED_REG_YMM24:
627 case XED_REG_YMM25:
628 case XED_REG_YMM26:
629 case XED_REG_YMM27:
630 case XED_REG_YMM28:
631 case XED_REG_YMM29:
632 case XED_REG_YMM30:
633 case XED_REG_YMM31:
634 case XED_REG_ZMM0:
635 case XED_REG_ZMM1:
636 case XED_REG_ZMM2:
637 case XED_REG_ZMM3:
638 case XED_REG_ZMM4:
639 case XED_REG_ZMM5:
640 case XED_REG_ZMM6:
641 case XED_REG_ZMM7:
642 case XED_REG_ZMM8:
643 case XED_REG_ZMM9:
644 case XED_REG_ZMM10:
645 case XED_REG_ZMM11:
646 case XED_REG_ZMM12:
647 case XED_REG_ZMM13:
648 case XED_REG_ZMM14:
649 case XED_REG_ZMM15:
650 case XED_REG_ZMM16:
651 case XED_REG_ZMM17:
652 case XED_REG_ZMM18:
653 case XED_REG_ZMM19:
654 case XED_REG_ZMM20:
655 case XED_REG_ZMM21:
656 case XED_REG_ZMM22:
657 case XED_REG_ZMM23:
658 case XED_REG_ZMM24:
659 case XED_REG_ZMM25:
660 case XED_REG_ZMM26:
661 case XED_REG_ZMM27:
662 case XED_REG_ZMM28:
663 case XED_REG_ZMM29:
664 case XED_REG_ZMM30:
665 case XED_REG_ZMM31:
666 case XED_REG_LAST:
667 default:
668 xed_assert(0);
669 }
670 */
671