1 /* $FreeBSD: head/sys/dev/usb/controller/xhci.c 278477 2015-02-09 21:47:12Z hselasky $ */
2 /*-
3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 *
30 * The XHCI 1.0 spec can be found at
31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
32 * and the USB 3.0 spec at
33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
34 */
35
36 /*
37 * A few words about the design implementation: This driver emulates
38 * the concept about TDs which is found in EHCI specification. This
39 * way we achieve that the USB controller drivers look similar to
40 * eachother which makes it easier to understand the code.
41 */
42
43 #include <sys/stdint.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/module.h>
51 #include <sys/lock.h>
52 #include <sys/condvar.h>
53 #include <sys/sysctl.h>
54 #include <sys/unistd.h>
55 #include <sys/callout.h>
56 #include <sys/malloc.h>
57 #include <sys/caps.h>
58
59 #include <bus/u4b/usb.h>
60 #include <bus/u4b/usbdi.h>
61
62 #define USB_DEBUG_VAR xhcidebug
63
64 #include <bus/u4b/usb_core.h>
65 #include <bus/u4b/usb_debug.h>
66 #include <bus/u4b/usb_busdma.h>
67 #include <bus/u4b/usb_process.h>
68 #include <bus/u4b/usb_transfer.h>
69 #include <bus/u4b/usb_device.h>
70 #include <bus/u4b/usb_hub.h>
71 #include <bus/u4b/usb_util.h>
72
73 #include <bus/u4b/usb_controller.h>
74 #include <bus/u4b/usb_bus.h>
75 #include <bus/u4b/controller/xhci.h>
76 #include <bus/u4b/controller/xhcireg.h>
77
78 #define XHCI_BUS2SC(bus) \
79 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
80 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
81
82 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
83
84 static int xhcistreams;
85 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW,
86 &xhcistreams, 0, "Set to enable streams mode support");
87 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
88
89 static int xhcipolling = 0;
90 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW,
91 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
92 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
93
94 #ifdef USB_DEBUG
95 static int xhcidebug = 0;
96 static int xhciroute = 0;
97 static int xhcidma32;
98
99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW,
100 &xhcidebug, 0, "Debug level");
101 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW,
103 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
104 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
105
106 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RW,
107 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
108 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
109
110 #else
111 #define xhciroute 0
112 #define xhcidma32 0
113 #endif
114
115 #define XHCI_INTR_ENDPT 1
116
117 struct xhci_std_temp {
118 struct xhci_softc *sc;
119 struct usb_page_cache *pc;
120 struct xhci_td *td;
121 struct xhci_td *td_next;
122 uint32_t len;
123 uint32_t offset;
124 uint32_t max_packet_size;
125 uint32_t average;
126 uint16_t isoc_delta;
127 uint16_t isoc_frame;
128 uint8_t shortpkt;
129 uint8_t multishort;
130 uint8_t last_frame;
131 uint8_t trb_type;
132 uint8_t direction;
133 uint8_t tbc;
134 uint8_t tlbpc;
135 uint8_t step_td;
136 uint8_t do_isoc_sync;
137 };
138
139 static void xhci_do_poll(struct usb_bus *);
140 static void xhci_device_done(struct usb_xfer *, usb_error_t);
141 static void xhci_root_intr(struct xhci_softc *);
142 static void xhci_free_device_ext(struct usb_device *);
143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
144 struct usb_endpoint_descriptor *);
145 static usb_proc_callback_t xhci_configure_msg;
146 static usb_error_t xhci_configure_device(struct usb_device *);
147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
150 uint8_t);
151 static usb_error_t xhci_configure_mask(struct usb_device *,
152 uint32_t, uint8_t);
153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
154 uint64_t, uint8_t);
155 static void xhci_endpoint_doorbell(struct usb_xfer *);
156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
159 #ifdef USB_DEBUG
160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
161 #endif
162
163 static const struct usb_bus_methods xhci_bus_methods;
164
165 #ifdef USB_DEBUG
166 static void
xhci_dump_trb(struct xhci_trb * trb)167 xhci_dump_trb(struct xhci_trb *trb)
168 {
169 DPRINTFN(5, "trb = %p\n", trb);
170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
173 }
174
175 static void
xhci_dump_endpoint(struct xhci_softc * sc,struct xhci_endp_ctx * pep)176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
177 {
178 DPRINTFN(5, "pep = %p\n", pep);
179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
186 }
187
188 static void
xhci_dump_device(struct xhci_softc * sc,struct xhci_slot_ctx * psl)189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
190 {
191 DPRINTFN(5, "psl = %p\n", psl);
192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
196 }
197 #endif
198
199 /*
200 * hw.usb.xhci.use_polling=1
201 */
202 uint8_t
xhci_use_polling(void)203 xhci_use_polling(void)
204 {
205 return (xhcipolling != 0);
206 }
207
208 static void
xhci_iterate_hw_softc(struct usb_bus * bus,usb_bus_mem_sub_cb_t * cb)209 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
210 {
211 struct xhci_softc *sc = XHCI_BUS2SC(bus);
212 uint8_t i;
213
214 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
215 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
216
217 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
218 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
219
220 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
221 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
222 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
223 }
224 }
225
226 static void
xhci_ctx_set_le32(struct xhci_softc * sc,volatile uint32_t * ptr,uint32_t val)227 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
228 {
229 if (sc->sc_ctx_is_64_byte) {
230 uint32_t offset;
231 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
232 /* all contexts are initially 32-bytes */
233 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
234 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
235 }
236 *ptr = htole32(val);
237 }
238
239 static uint32_t
xhci_ctx_get_le32(struct xhci_softc * sc,volatile uint32_t * ptr)240 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
241 {
242 if (sc->sc_ctx_is_64_byte) {
243 uint32_t offset;
244 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
245 /* all contexts are initially 32-bytes */
246 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
247 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
248 }
249 return (le32toh(*ptr));
250 }
251
252 static void
xhci_ctx_set_le64(struct xhci_softc * sc,volatile uint64_t * ptr,uint64_t val)253 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
254 {
255 if (sc->sc_ctx_is_64_byte) {
256 uint32_t offset;
257 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
258 /* all contexts are initially 32-bytes */
259 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
260 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
261 }
262 *ptr = htole64(val);
263 }
264
265 #ifdef USB_DEBUG
266 static uint64_t
xhci_ctx_get_le64(struct xhci_softc * sc,volatile uint64_t * ptr)267 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
268 {
269 if (sc->sc_ctx_is_64_byte) {
270 uint32_t offset;
271 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
272 /* all contexts are initially 32-bytes */
273 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
274 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
275 }
276 return (le64toh(*ptr));
277 }
278 #endif
279
280 static int
xhci_reset_command_queue_locked(struct xhci_softc * sc)281 xhci_reset_command_queue_locked(struct xhci_softc *sc)
282 {
283 struct usb_page_search buf_res;
284 struct xhci_hw_root *phwr;
285 uint64_t addr;
286 uint32_t temp;
287
288 DPRINTF("\n");
289
290 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
291 if (temp & XHCI_CRCR_LO_CRR) {
292 DPRINTF("Command ring running\n");
293 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
294
295 /*
296 * Try to abort the last command as per section
297 * 4.6.1.2 "Aborting a Command" of the XHCI
298 * specification:
299 */
300
301 /* stop and cancel */
302 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
303 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
304
305 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
306 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
307
308 /* wait 250ms */
309 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 4);
310
311 /* check if command ring is still running */
312 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
313 if (temp & XHCI_CRCR_LO_CRR) {
314 DPRINTF("Command ring still running\n");
315 return (USB_ERR_IOERROR);
316 }
317 }
318
319 /* reset command ring */
320 sc->sc_command_ccs = 1;
321 sc->sc_command_idx = 0;
322
323 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
324
325 /* set up command ring control base address */
326 addr = buf_res.physaddr;
327 phwr = buf_res.buffer;
328 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
329
330 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
331
332 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
333 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
334
335 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
336
337 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
338 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
339
340 return (0);
341 }
342
343 usb_error_t
xhci_start_controller(struct xhci_softc * sc)344 xhci_start_controller(struct xhci_softc *sc)
345 {
346 struct usb_page_search buf_res;
347 struct xhci_hw_root *phwr;
348 struct xhci_dev_ctx_addr *pdctxa;
349 uint64_t addr;
350 uint32_t temp;
351 uint16_t i;
352
353 DPRINTF("\n");
354
355 sc->sc_event_ccs = 1;
356 sc->sc_event_idx = 0;
357 sc->sc_command_ccs = 1;
358 sc->sc_command_idx = 0;
359
360 /* Reset controller */
361 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
362
363 for (i = 0; i != 100; i++) {
364 usb_pause_mtx(NULL, hz / 100);
365 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
366 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
367 if (!temp)
368 break;
369 }
370
371 if (temp) {
372 device_printf(sc->sc_bus.parent, "Controller "
373 "reset timeout.\n");
374 return (USB_ERR_IOERROR);
375 }
376
377 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
378 device_printf(sc->sc_bus.parent, "Controller does "
379 "not support 4K page size.\n");
380 return (USB_ERR_IOERROR);
381 }
382
383 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
384
385 i = XHCI_HCS1_N_PORTS(temp);
386
387 if (i == 0) {
388 device_printf(sc->sc_bus.parent, "Invalid number "
389 "of ports: %u\n", i);
390 return (USB_ERR_IOERROR);
391 }
392
393 sc->sc_noport = i;
394 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
395
396 if (sc->sc_noslot > XHCI_MAX_DEVICES)
397 sc->sc_noslot = XHCI_MAX_DEVICES;
398
399 /* set up number of device slots */
400
401 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
402 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
403
404 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
405
406 DPRINTF("Max slots: %u\n", sc->sc_noslot);
407
408 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
409
410 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
411
412 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
413 device_printf(sc->sc_bus.parent, "XHCI request "
414 "too many scratchpads\n");
415 return (USB_ERR_NOMEM);
416 }
417
418 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
419
420 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
421
422 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
423 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
424
425 temp = XREAD4(sc, oper, XHCI_USBSTS);
426
427 /* clear interrupts */
428 XWRITE4(sc, oper, XHCI_USBSTS, temp);
429 /* disable all device notifications */
430 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
431
432 /* set up device context base address */
433 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
434 pdctxa = buf_res.buffer;
435 memset(pdctxa, 0, sizeof(*pdctxa));
436
437 addr = buf_res.physaddr;
438 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
439
440 /* slot 0 points to the table of scratchpad pointers */
441 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
442
443 for (i = 0; i != sc->sc_noscratch; i++) {
444 struct usb_page_search buf_scp;
445 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
446 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
447 }
448
449 addr = buf_res.physaddr;
450
451 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
452 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
453 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
454 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
455
456 /* Setup event table size */
457
458 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
459
460 DPRINTF("HCS2=0x%08x\n", temp);
461
462 temp = XHCI_HCS2_ERST_MAX(temp);
463 temp = 1U << temp;
464 if (temp > XHCI_MAX_RSEG)
465 temp = XHCI_MAX_RSEG;
466
467 sc->sc_erst_max = temp;
468
469 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
470 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
471
472 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
473
474 /* Check if we should use the default IMOD value */
475 if (sc->sc_imod_default == 0)
476 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
477
478 /* Setup interrupt rate */
479 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
480
481 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
482
483 phwr = buf_res.buffer;
484 addr = buf_res.physaddr;
485 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
486
487 /* reset hardware root structure */
488 memset(phwr, 0, sizeof(*phwr));
489
490 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
491 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
492
493 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
494
495 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
496 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
497
498 addr = buf_res.physaddr;
499
500 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
501
502 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
503 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
504
505 /* Setup interrupter registers */
506
507 if (xhci_use_polling() == 0) {
508 temp = XREAD4(sc, runt, XHCI_IMAN(0));
509 temp |= XHCI_IMAN_INTR_ENA;
510 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
511 }
512
513 /* set up command ring control base address */
514 addr = buf_res.physaddr;
515 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
516
517 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
518
519 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
520 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
521
522 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
523
524 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
525
526 /* Go! */
527 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
528 XHCI_CMD_INTE | XHCI_CMD_HSEE);
529
530 for (i = 0; i != 100; i++) {
531 usb_pause_mtx(NULL, hz / 100);
532 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
533 if (!temp)
534 break;
535 }
536 if (temp) {
537 XWRITE4(sc, oper, XHCI_USBCMD, 0);
538 device_printf(sc->sc_bus.parent, "Run timeout.\n");
539 return (USB_ERR_IOERROR);
540 }
541
542 /* catch any lost interrupts */
543 xhci_do_poll(&sc->sc_bus);
544
545 if (sc->sc_port_route != NULL) {
546 /* Route all ports to the XHCI by default */
547 sc->sc_port_route(sc->sc_bus.parent,
548 ~xhciroute, xhciroute);
549 }
550 return (0);
551 }
552
553 usb_error_t
xhci_halt_controller(struct xhci_softc * sc)554 xhci_halt_controller(struct xhci_softc *sc)
555 {
556 uint32_t temp;
557 uint16_t i;
558
559 DPRINTF("\n");
560
561 sc->sc_event_ccs = 1;
562 sc->sc_event_idx = 0;
563 sc->sc_command_ccs = 1;
564 sc->sc_command_idx = 0;
565
566 /* Halt controller */
567 XWRITE4(sc, oper, XHCI_USBCMD, 0);
568
569 for (i = 0; i != 100; i++) {
570 usb_pause_mtx(NULL, hz / 100);
571 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
572 if (temp)
573 break;
574 }
575
576 if (!temp) {
577 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
578 return (USB_ERR_IOERROR);
579 }
580 return (0);
581 }
582
583 usb_error_t
xhci_init(struct xhci_softc * sc,device_t self,uint8_t dma32)584 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
585 {
586 uint32_t temp;
587
588 DPRINTF("\n");
589
590 /* initialise some bus fields */
591 sc->sc_bus.parent = self;
592
593 /* set the bus revision */
594 sc->sc_bus.usbrev = USB_REV_3_0;
595
596 /* set up the bus struct */
597 sc->sc_bus.methods = &xhci_bus_methods;
598
599 /* set up devices array */
600 sc->sc_bus.devices = sc->sc_devices;
601 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
602
603 /* set default cycle state in case of early interrupts */
604 sc->sc_event_ccs = 1;
605 sc->sc_command_ccs = 1;
606
607 /* set up bus space offsets */
608 sc->sc_capa_off = 0;
609 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
610 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
611 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
612
613 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
614 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
615 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
616
617 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
618
619 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
620
621 DPRINTF("HCS0 = 0x%08x\n", temp);
622
623 /* set up context size */
624 if (XHCI_HCS0_CSZ(temp)) {
625 sc->sc_ctx_is_64_byte = 1;
626 } else {
627 sc->sc_ctx_is_64_byte = 0;
628 }
629
630 /* get DMA bits */
631 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
632 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
633
634 device_printf(self, "%d bytes context size, %d-bit DMA\n",
635 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
636
637 /* get all DMA memory */
638 if (usb_bus_mem_alloc_all(&sc->sc_bus,
639 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
640 return (ENOMEM);
641 }
642
643 /* setup command queue mutex and condition varible */
644 cv_init(&sc->sc_cmd_cv, "CMDQ");
645 lockinit(&sc->sc_cmd_lock, "CMDQ lock", 0, LK_CANRECURSE);
646
647 /* set up command queue mutex and condition varible */
648 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
649 sc->sc_config_msg[0].bus = &sc->sc_bus;
650 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
651 sc->sc_config_msg[1].bus = &sc->sc_bus;
652
653 return (0);
654 }
655
656 void
xhci_uninit(struct xhci_softc * sc)657 xhci_uninit(struct xhci_softc *sc)
658 {
659 /*
660 * NOTE: At this point the control transfer process is gone
661 * and "xhci_configure_msg" is no longer called. Consequently
662 * waiting for the configuration messages to complete is not
663 * needed.
664 */
665 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
666
667 cv_destroy(&sc->sc_cmd_cv);
668 lockuninit(&sc->sc_cmd_lock);
669 }
670
671 static void
xhci_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)672 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
673 {
674 struct xhci_softc *sc = XHCI_BUS2SC(bus);
675
676 switch (state) {
677 case USB_HW_POWER_SUSPEND:
678 DPRINTF("Stopping the XHCI\n");
679 xhci_halt_controller(sc);
680 break;
681 case USB_HW_POWER_SHUTDOWN:
682 DPRINTF("Stopping the XHCI\n");
683 xhci_halt_controller(sc);
684 break;
685 case USB_HW_POWER_RESUME:
686 DPRINTF("Starting the XHCI\n");
687 xhci_start_controller(sc);
688 break;
689 default:
690 break;
691 }
692 }
693
694 static usb_error_t
xhci_generic_done_sub(struct usb_xfer * xfer)695 xhci_generic_done_sub(struct usb_xfer *xfer)
696 {
697 struct xhci_td *td;
698 struct xhci_td *td_alt_next;
699 uint32_t len;
700 uint8_t status;
701
702 td = xfer->td_transfer_cache;
703 td_alt_next = td->alt_next;
704
705 if (xfer->aframes != xfer->nframes)
706 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
707
708 while (1) {
709
710 usb_pc_cpu_invalidate(td->page_cache);
711
712 status = td->status;
713 len = td->remainder;
714
715 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
716 xfer, (unsigned int)xfer->aframes,
717 (unsigned int)xfer->nframes,
718 (unsigned int)len, (unsigned int)td->len,
719 (unsigned int)status);
720
721 /*
722 * Verify the status length and
723 * add the length to "frlengths[]":
724 */
725 if (len > td->len) {
726 /* should not happen */
727 DPRINTF("Invalid status length, "
728 "0x%04x/0x%04x bytes\n", len, td->len);
729 status = XHCI_TRB_ERROR_LENGTH;
730 } else if (xfer->aframes != xfer->nframes) {
731 xfer->frlengths[xfer->aframes] += td->len - len;
732 }
733 /* Check for last transfer */
734 if (((void *)td) == xfer->td_transfer_last) {
735 td = NULL;
736 break;
737 }
738 /* Check for transfer error */
739 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
740 status != XHCI_TRB_ERROR_SUCCESS) {
741 /* the transfer is finished */
742 td = NULL;
743 break;
744 }
745 /* Check for short transfer */
746 if (len > 0) {
747 if (xfer->flags_int.short_frames_ok ||
748 xfer->flags_int.isochronous_xfr ||
749 xfer->flags_int.control_xfr) {
750 /* follow alt next */
751 td = td->alt_next;
752 } else {
753 /* the transfer is finished */
754 td = NULL;
755 }
756 break;
757 }
758 td = td->obj_next;
759
760 if (td->alt_next != td_alt_next) {
761 /* this USB frame is complete */
762 break;
763 }
764 }
765
766 /* update transfer cache */
767
768 xfer->td_transfer_cache = td;
769
770 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
771 (status != XHCI_TRB_ERROR_SHORT_PKT &&
772 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
773 USB_ERR_NORMAL_COMPLETION);
774 }
775
776 static void
xhci_generic_done(struct usb_xfer * xfer)777 xhci_generic_done(struct usb_xfer *xfer)
778 {
779 usb_error_t err = 0;
780
781 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
782 xfer, xfer->endpoint);
783
784 /* reset scanner */
785
786 xfer->td_transfer_cache = xfer->td_transfer_first;
787
788 if (xfer->flags_int.control_xfr) {
789
790 if (xfer->flags_int.control_hdr)
791 err = xhci_generic_done_sub(xfer);
792
793 xfer->aframes = 1;
794
795 if (xfer->td_transfer_cache == NULL)
796 goto done;
797 }
798
799 while (xfer->aframes != xfer->nframes) {
800
801 err = xhci_generic_done_sub(xfer);
802 xfer->aframes++;
803
804 if (xfer->td_transfer_cache == NULL)
805 goto done;
806 }
807
808 if (xfer->flags_int.control_xfr &&
809 !xfer->flags_int.control_act)
810 err = xhci_generic_done_sub(xfer);
811 done:
812 /* transfer is complete */
813 xhci_device_done(xfer, err);
814 }
815
816 static void
xhci_activate_transfer(struct usb_xfer * xfer)817 xhci_activate_transfer(struct usb_xfer *xfer)
818 {
819 struct xhci_td *td;
820
821 td = xfer->td_transfer_cache;
822
823 usb_pc_cpu_invalidate(td->page_cache);
824
825 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
826
827 /* activate the transfer */
828
829 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
830 usb_pc_cpu_flush(td->page_cache);
831
832 xhci_endpoint_doorbell(xfer);
833 }
834 }
835
836 static void
xhci_skip_transfer(struct usb_xfer * xfer)837 xhci_skip_transfer(struct usb_xfer *xfer)
838 {
839 struct xhci_td *td;
840 struct xhci_td *td_last;
841
842 td = xfer->td_transfer_cache;
843 td_last = xfer->td_transfer_last;
844
845 td = td->alt_next;
846
847 usb_pc_cpu_invalidate(td->page_cache);
848
849 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
850
851 usb_pc_cpu_invalidate(td_last->page_cache);
852
853 /* copy LINK TRB to current waiting location */
854
855 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
856 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
857 usb_pc_cpu_flush(td->page_cache);
858
859 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
860 usb_pc_cpu_flush(td->page_cache);
861
862 xhci_endpoint_doorbell(xfer);
863 }
864 }
865
866 /*------------------------------------------------------------------------*
867 * xhci_check_transfer
868 *------------------------------------------------------------------------*/
869 static void
xhci_check_transfer(struct xhci_softc * sc,struct xhci_trb * trb)870 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
871 {
872 struct xhci_endpoint_ext *pepext;
873 int64_t offset;
874 uint64_t td_event;
875 uint32_t temp;
876 uint32_t remainder;
877 uint16_t stream_id;
878 uint16_t i;
879 uint8_t status;
880 uint8_t halted;
881 uint8_t epno;
882 uint8_t index;
883
884 /* decode TRB */
885 td_event = le64toh(trb->qwTrb0);
886 temp = le32toh(trb->dwTrb2);
887
888 remainder = XHCI_TRB_2_REM_GET(temp);
889 status = XHCI_TRB_2_ERROR_GET(temp);
890 stream_id = XHCI_TRB_2_STREAM_GET(temp);
891
892 temp = le32toh(trb->dwTrb3);
893 epno = XHCI_TRB_3_EP_GET(temp);
894 index = XHCI_TRB_3_SLOT_GET(temp);
895
896 /* check if error means halted */
897 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
898 status != XHCI_TRB_ERROR_SUCCESS);
899
900 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
901 index, epno, stream_id, remainder, status);
902
903 if (index > sc->sc_noslot) {
904 DPRINTF("Invalid slot.\n");
905 return;
906 }
907
908 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
909 DPRINTF("Invalid endpoint.\n");
910 return;
911 }
912
913 pepext = &sc->sc_hw.devs[index].endp[epno];
914
915 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
916 stream_id = 0;
917 DPRINTF("stream_id=0\n");
918 } else if (stream_id >= XHCI_MAX_STREAMS) {
919 DPRINTF("Invalid stream ID.\n");
920 return;
921 }
922
923 /* try to find the USB transfer that generated the event */
924 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
925 struct usb_xfer *xfer;
926 struct xhci_td *td;
927
928 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
929 if (xfer == NULL)
930 continue;
931
932 td = xfer->td_transfer_cache;
933
934 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
935 (long long)td_event,
936 (long long)td->td_self,
937 (long long)td->td_self + sizeof(td->td_trb));
938
939 /*
940 * NOTE: Some XHCI implementations might not trigger
941 * an event on the last LINK TRB so we need to
942 * consider both the last and second last event
943 * address as conditions for a successful transfer.
944 *
945 * NOTE: We assume that the XHCI will only trigger one
946 * event per chain of TRBs.
947 */
948
949 offset = td_event - td->td_self;
950
951 if (offset >= 0 &&
952 offset < (int64_t)sizeof(td->td_trb)) {
953
954 usb_pc_cpu_invalidate(td->page_cache);
955
956 /* compute rest of remainder, if any */
957 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
958 temp = le32toh(td->td_trb[i].dwTrb2);
959 remainder += XHCI_TRB_2_BYTES_GET(temp);
960 }
961
962 DPRINTFN(5, "New remainder: %u\n", remainder);
963
964 /* clear isochronous transfer errors */
965 if (xfer->flags_int.isochronous_xfr) {
966 if (halted) {
967 halted = 0;
968 status = XHCI_TRB_ERROR_SUCCESS;
969 remainder = td->len;
970 }
971 }
972
973 /* "td->remainder" is verified later */
974 td->remainder = remainder;
975 td->status = status;
976
977 usb_pc_cpu_flush(td->page_cache);
978
979 /*
980 * 1) Last transfer descriptor makes the
981 * transfer done
982 */
983 if (((void *)td) == xfer->td_transfer_last) {
984 DPRINTF("TD is last\n");
985 xhci_generic_done(xfer);
986 break;
987 }
988
989 /*
990 * 2) Any kind of error makes the transfer
991 * done
992 */
993 if (halted) {
994 DPRINTF("TD has I/O error\n");
995 xhci_generic_done(xfer);
996 break;
997 }
998
999 /*
1000 * 3) If there is no alternate next transfer,
1001 * a short packet also makes the transfer done
1002 */
1003 if (td->remainder > 0) {
1004 if (td->alt_next == NULL) {
1005 DPRINTF(
1006 "short TD has no alternate next\n");
1007 xhci_generic_done(xfer);
1008 break;
1009 }
1010 DPRINTF("TD has short pkt\n");
1011 if (xfer->flags_int.short_frames_ok ||
1012 xfer->flags_int.isochronous_xfr ||
1013 xfer->flags_int.control_xfr) {
1014 /* follow the alt next */
1015 xfer->td_transfer_cache = td->alt_next;
1016 xhci_activate_transfer(xfer);
1017 break;
1018 }
1019 xhci_skip_transfer(xfer);
1020 xhci_generic_done(xfer);
1021 break;
1022 }
1023
1024 /*
1025 * 4) Transfer complete - go to next TD
1026 */
1027 DPRINTF("Following next TD\n");
1028 xfer->td_transfer_cache = td->obj_next;
1029 xhci_activate_transfer(xfer);
1030 break; /* there should only be one match */
1031 }
1032 }
1033 }
1034
1035 static int
xhci_check_command(struct xhci_softc * sc,struct xhci_trb * trb)1036 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1037 {
1038 if (sc->sc_cmd_addr == trb->qwTrb0) {
1039 DPRINTF("Received command event\n");
1040 sc->sc_cmd_result[0] = trb->dwTrb2;
1041 sc->sc_cmd_result[1] = trb->dwTrb3;
1042 cv_signal(&sc->sc_cmd_cv);
1043 return (1); /* command match */
1044 }
1045 return (0);
1046 }
1047
1048 static int
xhci_interrupt_poll(struct xhci_softc * sc)1049 xhci_interrupt_poll(struct xhci_softc *sc)
1050 {
1051 struct usb_page_search buf_res;
1052 struct xhci_hw_root *phwr;
1053 uint64_t addr;
1054 uint32_t temp;
1055 int retval = 0;
1056 uint16_t i;
1057 uint8_t event;
1058 uint8_t j;
1059 uint8_t k;
1060 uint8_t t;
1061
1062 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1063
1064 phwr = buf_res.buffer;
1065
1066 /* Receive any events */
1067
1068 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1069
1070 i = sc->sc_event_idx;
1071 j = sc->sc_event_ccs;
1072 t = 2;
1073
1074 while (1) {
1075
1076 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1077
1078 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1079
1080 if (j != k)
1081 break;
1082
1083 event = XHCI_TRB_3_TYPE_GET(temp);
1084
1085 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1086 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1087 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1088 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1089
1090 switch (event) {
1091 case XHCI_TRB_EVENT_TRANSFER:
1092 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1093 break;
1094 case XHCI_TRB_EVENT_CMD_COMPLETE:
1095 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1096 break;
1097 default:
1098 DPRINTF("Unhandled event = %u\n", event);
1099 break;
1100 }
1101
1102 i++;
1103
1104 if (i == XHCI_MAX_EVENTS) {
1105 i = 0;
1106 j ^= 1;
1107
1108 /* check for timeout */
1109 if (!--t)
1110 break;
1111 }
1112 }
1113
1114 sc->sc_event_idx = i;
1115 sc->sc_event_ccs = j;
1116
1117 /*
1118 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1119 * latched. That means to activate the register we need to
1120 * write both the low and high double word of the 64-bit
1121 * register.
1122 */
1123
1124 addr = buf_res.physaddr;
1125 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1126
1127 /* try to clear busy bit */
1128 addr |= XHCI_ERDP_LO_BUSY;
1129
1130 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1131 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1132
1133 return (retval);
1134 }
1135
1136 static usb_error_t
xhci_do_command(struct xhci_softc * sc,struct xhci_trb * trb,uint16_t timeout_ms)1137 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1138 uint16_t timeout_ms)
1139 {
1140 struct usb_page_search buf_res;
1141 struct xhci_hw_root *phwr;
1142 uint64_t addr;
1143 uint32_t temp;
1144 uint8_t i;
1145 uint8_t j;
1146 uint8_t timeout = 0;
1147 int err;
1148
1149 XHCI_CMD_ASSERT_LOCKED(sc);
1150
1151 /* get hardware root structure */
1152
1153 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1154
1155 phwr = buf_res.buffer;
1156
1157 /* Queue command */
1158
1159 USB_BUS_LOCK(&sc->sc_bus);
1160 retry:
1161 i = sc->sc_command_idx;
1162 j = sc->sc_command_ccs;
1163
1164 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1165 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1166 (long long)le64toh(trb->qwTrb0),
1167 (long)le32toh(trb->dwTrb2),
1168 (long)le32toh(trb->dwTrb3));
1169
1170 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1171 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1172
1173 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1174
1175 temp = trb->dwTrb3;
1176
1177 if (j)
1178 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1179 else
1180 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1181
1182 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1183
1184 phwr->hwr_commands[i].dwTrb3 = temp;
1185
1186 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1187
1188 addr = buf_res.physaddr;
1189 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1190
1191 sc->sc_cmd_addr = htole64(addr);
1192
1193 i++;
1194
1195 if (i == (XHCI_MAX_COMMANDS - 1)) {
1196
1197 if (j) {
1198 temp = htole32(XHCI_TRB_3_TC_BIT |
1199 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1200 XHCI_TRB_3_CYCLE_BIT);
1201 } else {
1202 temp = htole32(XHCI_TRB_3_TC_BIT |
1203 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1204 }
1205
1206 phwr->hwr_commands[i].dwTrb3 = temp;
1207
1208 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1209
1210 i = 0;
1211 j ^= 1;
1212 }
1213
1214 sc->sc_command_idx = i;
1215 sc->sc_command_ccs = j;
1216
1217 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1218
1219 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_lock,
1220 USB_MS_TO_TICKS(timeout_ms));
1221
1222 /*
1223 * In some error cases event interrupts are not generated.
1224 * Poll one time to see if the command has completed.
1225 */
1226 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1227 DPRINTF("Command was completed when polling\n");
1228 err = 0;
1229 }
1230 if (err != 0) {
1231 DPRINTF("Command timeout!\n");
1232 /*
1233 * After some weeks of continuous operation, it has
1234 * been observed that the ASMedia Technology, ASM1042
1235 * SuperSpeed USB Host Controller can suddenly stop
1236 * accepting commands via the command queue. Try to
1237 * first reset the command queue. If that fails do a
1238 * host controller reset.
1239 */
1240 if (timeout == 0 &&
1241 xhci_reset_command_queue_locked(sc) == 0) {
1242 temp = le32toh(trb->dwTrb3);
1243
1244 /*
1245 * Avoid infinite XHCI reset loops if the set
1246 * address command fails to respond due to a
1247 * non-enumerating device:
1248 */
1249 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1250 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1251 DPRINTF("Set address timeout\n");
1252 } else {
1253 timeout = 1;
1254 goto retry;
1255 }
1256 } else {
1257 DPRINTF("Controller reset!\n");
1258 usb_bus_reset_async_locked(&sc->sc_bus);
1259 }
1260 err = USB_ERR_TIMEOUT;
1261 trb->dwTrb2 = 0;
1262 trb->dwTrb3 = 0;
1263 } else {
1264 temp = le32toh(sc->sc_cmd_result[0]);
1265 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1266 err = USB_ERR_IOERROR;
1267
1268 trb->dwTrb2 = sc->sc_cmd_result[0];
1269 trb->dwTrb3 = sc->sc_cmd_result[1];
1270 }
1271
1272 USB_BUS_UNLOCK(&sc->sc_bus);
1273
1274 return (err);
1275 }
1276
1277 #if 0
1278 static usb_error_t
1279 xhci_cmd_nop(struct xhci_softc *sc)
1280 {
1281 struct xhci_trb trb;
1282 uint32_t temp;
1283
1284 DPRINTF("\n");
1285
1286 trb.qwTrb0 = 0;
1287 trb.dwTrb2 = 0;
1288 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1289
1290 trb.dwTrb3 = htole32(temp);
1291
1292 return (xhci_do_command(sc, &trb, 100 /* ms */));
1293 }
1294 #endif
1295
1296 static usb_error_t
xhci_cmd_enable_slot(struct xhci_softc * sc,uint8_t * pslot)1297 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1298 {
1299 struct xhci_trb trb;
1300 uint32_t temp;
1301 usb_error_t err;
1302
1303 DPRINTF("\n");
1304
1305 trb.qwTrb0 = 0;
1306 trb.dwTrb2 = 0;
1307 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1308
1309 err = xhci_do_command(sc, &trb, 100 /* ms */);
1310 if (err)
1311 goto done;
1312
1313 temp = le32toh(trb.dwTrb3);
1314
1315 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1316
1317 done:
1318 return (err);
1319 }
1320
1321 static usb_error_t
xhci_cmd_disable_slot(struct xhci_softc * sc,uint8_t slot_id)1322 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1323 {
1324 struct xhci_trb trb;
1325 uint32_t temp;
1326
1327 DPRINTF("\n");
1328
1329 trb.qwTrb0 = 0;
1330 trb.dwTrb2 = 0;
1331 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1332 XHCI_TRB_3_SLOT_SET(slot_id);
1333
1334 trb.dwTrb3 = htole32(temp);
1335
1336 return (xhci_do_command(sc, &trb, 100 /* ms */));
1337 }
1338
1339 static usb_error_t
xhci_cmd_set_address(struct xhci_softc * sc,uint64_t input_ctx,uint8_t bsr,uint8_t slot_id)1340 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1341 uint8_t bsr, uint8_t slot_id)
1342 {
1343 struct xhci_trb trb;
1344 uint32_t temp;
1345
1346 DPRINTF("\n");
1347
1348 trb.qwTrb0 = htole64(input_ctx);
1349 trb.dwTrb2 = 0;
1350 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1351 XHCI_TRB_3_SLOT_SET(slot_id);
1352
1353 if (bsr)
1354 temp |= XHCI_TRB_3_BSR_BIT;
1355
1356 trb.dwTrb3 = htole32(temp);
1357
1358 return (xhci_do_command(sc, &trb, 500 /* ms */));
1359 }
1360
1361 static usb_error_t
xhci_set_address(struct usb_device * udev,struct lock * lock,uint16_t address)1362 xhci_set_address(struct usb_device *udev, struct lock *lock, uint16_t address)
1363 {
1364 struct usb_page_search buf_inp;
1365 struct usb_page_search buf_dev;
1366 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1367 struct xhci_hw_dev *hdev;
1368 struct xhci_dev_ctx *pdev;
1369 struct xhci_endpoint_ext *pepext;
1370 uint32_t temp;
1371 uint16_t mps;
1372 usb_error_t err;
1373 uint8_t index;
1374
1375 /* the root HUB case is not handled here */
1376 if (udev->parent_hub == NULL)
1377 return (USB_ERR_INVAL);
1378
1379 index = udev->controller_slot_id;
1380
1381 hdev = &sc->sc_hw.devs[index];
1382
1383 if (lock != NULL)
1384 lockmgr(lock, LK_RELEASE);
1385
1386 XHCI_CMD_LOCK(sc);
1387
1388 switch (hdev->state) {
1389 case XHCI_ST_DEFAULT:
1390 case XHCI_ST_ENABLED:
1391
1392 hdev->state = XHCI_ST_ENABLED;
1393
1394 /* set configure mask to slot and EP0 */
1395 xhci_configure_mask(udev, 3, 0);
1396
1397 /* configure input slot context structure */
1398 err = xhci_configure_device(udev);
1399
1400 if (err != 0) {
1401 DPRINTF("Could not configure device\n");
1402 break;
1403 }
1404
1405 /* configure input endpoint context structure */
1406 switch (udev->speed) {
1407 case USB_SPEED_LOW:
1408 case USB_SPEED_FULL:
1409 mps = 8;
1410 break;
1411 case USB_SPEED_HIGH:
1412 mps = 64;
1413 break;
1414 default:
1415 mps = 512;
1416 break;
1417 }
1418
1419 pepext = xhci_get_endpoint_ext(udev,
1420 &udev->ctrl_ep_desc);
1421
1422 /* ensure the control endpoint is setup again */
1423 USB_BUS_LOCK(udev->bus);
1424 pepext->trb_halted = 1;
1425 pepext->trb_running = 0;
1426 USB_BUS_UNLOCK(udev->bus);
1427
1428 err = xhci_configure_endpoint(udev,
1429 &udev->ctrl_ep_desc, pepext,
1430 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1431
1432 if (err != 0) {
1433 DPRINTF("Could not configure default endpoint\n");
1434 break;
1435 }
1436
1437 /* execute set address command */
1438 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1439
1440 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1441 (address == 0), index);
1442
1443 if (err != 0) {
1444 temp = le32toh(sc->sc_cmd_result[0]);
1445 if (address == 0 && sc->sc_port_route != NULL &&
1446 XHCI_TRB_2_ERROR_GET(temp) ==
1447 XHCI_TRB_ERROR_PARAMETER) {
1448 /* LynxPoint XHCI - ports are not switchable */
1449 /* Un-route all ports from the XHCI */
1450 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1451 }
1452 DPRINTF("Could not set address "
1453 "for slot %u.\n", index);
1454 if (address != 0)
1455 break;
1456 }
1457
1458 /* update device address to new value */
1459
1460 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1461 pdev = buf_dev.buffer;
1462 usb_pc_cpu_invalidate(&hdev->device_pc);
1463
1464 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1465 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1466
1467 /* update device state to new value */
1468
1469 if (address != 0)
1470 hdev->state = XHCI_ST_ADDRESSED;
1471 else
1472 hdev->state = XHCI_ST_DEFAULT;
1473 break;
1474
1475 default:
1476 DPRINTF("Wrong state for set address.\n");
1477 err = USB_ERR_IOERROR;
1478 break;
1479 }
1480 XHCI_CMD_UNLOCK(sc);
1481
1482 if (lock != NULL)
1483 lockmgr(lock, LK_EXCLUSIVE);
1484
1485 return (err);
1486 }
1487
1488 static usb_error_t
xhci_cmd_configure_ep(struct xhci_softc * sc,uint64_t input_ctx,uint8_t deconfigure,uint8_t slot_id)1489 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1490 uint8_t deconfigure, uint8_t slot_id)
1491 {
1492 struct xhci_trb trb;
1493 uint32_t temp;
1494
1495 DPRINTF("\n");
1496
1497 trb.qwTrb0 = htole64(input_ctx);
1498 trb.dwTrb2 = 0;
1499 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1500 XHCI_TRB_3_SLOT_SET(slot_id);
1501
1502 if (deconfigure)
1503 temp |= XHCI_TRB_3_DCEP_BIT;
1504
1505 trb.dwTrb3 = htole32(temp);
1506
1507 return (xhci_do_command(sc, &trb, 100 /* ms */));
1508 }
1509
1510 static usb_error_t
xhci_cmd_evaluate_ctx(struct xhci_softc * sc,uint64_t input_ctx,uint8_t slot_id)1511 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1512 uint8_t slot_id)
1513 {
1514 struct xhci_trb trb;
1515 uint32_t temp;
1516
1517 DPRINTF("\n");
1518
1519 trb.qwTrb0 = htole64(input_ctx);
1520 trb.dwTrb2 = 0;
1521 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1522 XHCI_TRB_3_SLOT_SET(slot_id);
1523 trb.dwTrb3 = htole32(temp);
1524
1525 return (xhci_do_command(sc, &trb, 100 /* ms */));
1526 }
1527
1528 static usb_error_t
xhci_cmd_reset_ep(struct xhci_softc * sc,uint8_t preserve,uint8_t ep_id,uint8_t slot_id)1529 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1530 uint8_t ep_id, uint8_t slot_id)
1531 {
1532 struct xhci_trb trb;
1533 uint32_t temp;
1534
1535 DPRINTF("\n");
1536
1537 trb.qwTrb0 = 0;
1538 trb.dwTrb2 = 0;
1539 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1540 XHCI_TRB_3_SLOT_SET(slot_id) |
1541 XHCI_TRB_3_EP_SET(ep_id);
1542
1543 if (preserve)
1544 temp |= XHCI_TRB_3_PRSV_BIT;
1545
1546 trb.dwTrb3 = htole32(temp);
1547
1548 return (xhci_do_command(sc, &trb, 100 /* ms */));
1549 }
1550
1551 static usb_error_t
xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc * sc,uint64_t dequeue_ptr,uint16_t stream_id,uint8_t ep_id,uint8_t slot_id)1552 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1553 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1554 {
1555 struct xhci_trb trb;
1556 uint32_t temp;
1557
1558 DPRINTF("\n");
1559
1560 trb.qwTrb0 = htole64(dequeue_ptr);
1561
1562 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1563 trb.dwTrb2 = htole32(temp);
1564
1565 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1566 XHCI_TRB_3_SLOT_SET(slot_id) |
1567 XHCI_TRB_3_EP_SET(ep_id);
1568 trb.dwTrb3 = htole32(temp);
1569
1570 return (xhci_do_command(sc, &trb, 100 /* ms */));
1571 }
1572
1573 static usb_error_t
xhci_cmd_stop_ep(struct xhci_softc * sc,uint8_t suspend,uint8_t ep_id,uint8_t slot_id)1574 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1575 uint8_t ep_id, uint8_t slot_id)
1576 {
1577 struct xhci_trb trb;
1578 uint32_t temp;
1579
1580 DPRINTF("\n");
1581
1582 trb.qwTrb0 = 0;
1583 trb.dwTrb2 = 0;
1584 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1585 XHCI_TRB_3_SLOT_SET(slot_id) |
1586 XHCI_TRB_3_EP_SET(ep_id);
1587
1588 if (suspend)
1589 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1590
1591 trb.dwTrb3 = htole32(temp);
1592
1593 return (xhci_do_command(sc, &trb, 100 /* ms */));
1594 }
1595
1596 static usb_error_t
xhci_cmd_reset_dev(struct xhci_softc * sc,uint8_t slot_id)1597 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1598 {
1599 struct xhci_trb trb;
1600 uint32_t temp;
1601
1602 DPRINTF("\n");
1603
1604 trb.qwTrb0 = 0;
1605 trb.dwTrb2 = 0;
1606 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1607 XHCI_TRB_3_SLOT_SET(slot_id);
1608
1609 trb.dwTrb3 = htole32(temp);
1610
1611 return (xhci_do_command(sc, &trb, 100 /* ms */));
1612 }
1613
1614 /*------------------------------------------------------------------------*
1615 * xhci_interrupt - XHCI interrupt handler
1616 *------------------------------------------------------------------------*/
1617 void
xhci_interrupt(struct xhci_softc * sc)1618 xhci_interrupt(struct xhci_softc *sc)
1619 {
1620 uint32_t status;
1621 uint32_t temp;
1622
1623 USB_BUS_LOCK(&sc->sc_bus);
1624
1625 status = XREAD4(sc, oper, XHCI_USBSTS);
1626
1627 /* acknowledge interrupts, if any */
1628 if (status != 0) {
1629 XWRITE4(sc, oper, XHCI_USBSTS, status);
1630 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1631 }
1632
1633 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1634
1635 /* force clearing of pending interrupts */
1636 if (temp & XHCI_IMAN_INTR_PEND)
1637 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1638
1639 /* check for event(s) */
1640 xhci_interrupt_poll(sc);
1641
1642 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1643 XHCI_STS_HSE | XHCI_STS_HCE)) {
1644
1645 if (status & XHCI_STS_PCD) {
1646 xhci_root_intr(sc);
1647 }
1648
1649 if (status & XHCI_STS_HCH) {
1650 kprintf("%s: host controller halted\n",
1651 __func__);
1652 }
1653
1654 if (status & XHCI_STS_HSE) {
1655 kprintf("%s: host system error\n",
1656 __func__);
1657 }
1658
1659 if (status & XHCI_STS_HCE) {
1660 kprintf("%s: host controller error\n",
1661 __func__);
1662 }
1663 }
1664 USB_BUS_UNLOCK(&sc->sc_bus);
1665 }
1666
1667 /*------------------------------------------------------------------------*
1668 * xhci_timeout - XHCI timeout handler
1669 *------------------------------------------------------------------------*/
1670 static void
xhci_timeout(void * arg)1671 xhci_timeout(void *arg)
1672 {
1673 struct usb_xfer *xfer = arg;
1674
1675 DPRINTF("xfer=%p\n", xfer);
1676
1677 USB_BUS_LOCK_ASSERT(xfer->xroot->bus);
1678
1679 /* transfer is transferred */
1680 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1681 }
1682
1683 static void
xhci_do_poll(struct usb_bus * bus)1684 xhci_do_poll(struct usb_bus *bus)
1685 {
1686 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1687
1688 USB_BUS_LOCK(&sc->sc_bus);
1689 xhci_interrupt_poll(sc);
1690 USB_BUS_UNLOCK(&sc->sc_bus);
1691 }
1692
1693 static void
xhci_setup_generic_chain_sub(struct xhci_std_temp * temp)1694 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1695 {
1696 struct usb_page_search buf_res;
1697 struct xhci_td *td;
1698 struct xhci_td *td_next;
1699 struct xhci_td *td_alt_next;
1700 struct xhci_td *td_first;
1701 uint32_t buf_offset;
1702 uint32_t average;
1703 uint32_t len_old;
1704 uint32_t npkt_off;
1705 uint32_t dword;
1706 uint8_t shortpkt_old;
1707 uint8_t precompute;
1708 uint8_t x;
1709
1710 td_alt_next = NULL;
1711 buf_offset = 0;
1712 shortpkt_old = temp->shortpkt;
1713 len_old = temp->len;
1714 npkt_off = 0;
1715 precompute = 1;
1716
1717 restart:
1718
1719 td = temp->td;
1720 td_next = td_first = temp->td_next;
1721
1722 while (1) {
1723
1724 if (temp->len == 0) {
1725
1726 if (temp->shortpkt)
1727 break;
1728
1729 /* send a Zero Length Packet, ZLP, last */
1730
1731 temp->shortpkt = 1;
1732 average = 0;
1733
1734 } else {
1735
1736 average = temp->average;
1737
1738 if (temp->len < average) {
1739 if (temp->len % temp->max_packet_size) {
1740 temp->shortpkt = 1;
1741 }
1742 average = temp->len;
1743 }
1744 }
1745
1746 if (td_next == NULL)
1747 panic("%s: out of XHCI transfer descriptors!", __func__);
1748
1749 /* get next TD */
1750
1751 td = td_next;
1752 td_next = td->obj_next;
1753
1754 /* check if we are pre-computing */
1755
1756 if (precompute) {
1757
1758 /* update remaining length */
1759
1760 temp->len -= average;
1761
1762 continue;
1763 }
1764 /* fill out current TD */
1765
1766 td->len = average;
1767 td->remainder = 0;
1768 td->status = 0;
1769
1770 /* update remaining length */
1771
1772 temp->len -= average;
1773
1774 /* reset TRB index */
1775
1776 x = 0;
1777
1778 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1779 /* immediate data */
1780
1781 if (average > 8)
1782 average = 8;
1783
1784 td->td_trb[0].qwTrb0 = 0;
1785
1786 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1787 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1788 average);
1789
1790 dword = XHCI_TRB_2_BYTES_SET(8) |
1791 XHCI_TRB_2_TDSZ_SET(0) |
1792 XHCI_TRB_2_IRQ_SET(0);
1793
1794 td->td_trb[0].dwTrb2 = htole32(dword);
1795
1796 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1797 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1798
1799 /* check wLength */
1800 if (td->td_trb[0].qwTrb0 &
1801 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1802 if (td->td_trb[0].qwTrb0 &
1803 htole64(XHCI_TRB_0_DIR_IN_MASK))
1804 dword |= XHCI_TRB_3_TRT_IN;
1805 else
1806 dword |= XHCI_TRB_3_TRT_OUT;
1807 }
1808
1809 td->td_trb[0].dwTrb3 = htole32(dword);
1810 #ifdef USB_DEBUG
1811 xhci_dump_trb(&td->td_trb[x]);
1812 #endif
1813 x++;
1814
1815 } else do {
1816
1817 uint32_t npkt;
1818
1819 /* fill out buffer pointers */
1820
1821 if (average == 0) {
1822 memset(&buf_res, 0, sizeof(buf_res));
1823 } else {
1824 usbd_get_page(temp->pc, temp->offset +
1825 buf_offset, &buf_res);
1826
1827 /* get length to end of page */
1828 if (buf_res.length > average)
1829 buf_res.length = average;
1830
1831 /* check for maximum length */
1832 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1833 buf_res.length = XHCI_TD_PAGE_SIZE;
1834
1835 npkt_off += buf_res.length;
1836 }
1837
1838 /* set up npkt */
1839 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1840 temp->max_packet_size;
1841
1842 if (npkt == 0)
1843 npkt = 1;
1844 else if (npkt > 31)
1845 npkt = 31;
1846
1847 /* fill out TRB's */
1848 td->td_trb[x].qwTrb0 =
1849 htole64((uint64_t)buf_res.physaddr);
1850
1851 dword =
1852 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1853 XHCI_TRB_2_TDSZ_SET(npkt) |
1854 XHCI_TRB_2_IRQ_SET(0);
1855
1856 td->td_trb[x].dwTrb2 = htole32(dword);
1857
1858 switch (temp->trb_type) {
1859 case XHCI_TRB_TYPE_ISOCH:
1860 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1861 XHCI_TRB_3_TBC_SET(temp->tbc) |
1862 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1863 if (td != td_first) {
1864 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1865 } else if (temp->do_isoc_sync != 0) {
1866 temp->do_isoc_sync = 0;
1867 /* wait until "isoc_frame" */
1868 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1869 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1870 } else {
1871 /* start data transfer at next interval */
1872 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1873 XHCI_TRB_3_ISO_SIA_BIT;
1874 }
1875 if (temp->direction == UE_DIR_IN)
1876 dword |= XHCI_TRB_3_ISP_BIT;
1877 break;
1878 case XHCI_TRB_TYPE_DATA_STAGE:
1879 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1880 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1881 if (temp->direction == UE_DIR_IN)
1882 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1883 /*
1884 * Section 3.2.9 in the XHCI
1885 * specification about control
1886 * transfers says that we should use a
1887 * normal-TRB if there are more TRBs
1888 * extending the data-stage
1889 * TRB. Update the "trb_type".
1890 */
1891 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1892 break;
1893 case XHCI_TRB_TYPE_STATUS_STAGE:
1894 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1895 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1896 if (temp->direction == UE_DIR_IN)
1897 dword |= XHCI_TRB_3_DIR_IN;
1898 break;
1899 default: /* XHCI_TRB_TYPE_NORMAL */
1900 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1901 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1902 if (temp->direction == UE_DIR_IN)
1903 dword |= XHCI_TRB_3_ISP_BIT;
1904 break;
1905 }
1906 td->td_trb[x].dwTrb3 = htole32(dword);
1907
1908 average -= buf_res.length;
1909 buf_offset += buf_res.length;
1910 #ifdef USB_DEBUG
1911 xhci_dump_trb(&td->td_trb[x]);
1912 #endif
1913 x++;
1914
1915 } while (average != 0);
1916
1917 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1918
1919 /* store number of data TRB's */
1920
1921 td->ntrb = x;
1922
1923 DPRINTF("NTRB=%u\n", x);
1924
1925 /* fill out link TRB */
1926
1927 if (td_next != NULL) {
1928 /* link the current TD with the next one */
1929 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1930 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1931 } else {
1932 /* this field will get updated later */
1933 DPRINTF("NOLINK\n");
1934 }
1935
1936 dword = XHCI_TRB_2_IRQ_SET(0);
1937
1938 td->td_trb[x].dwTrb2 = htole32(dword);
1939
1940 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1941 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1942 /*
1943 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1944 * frame only receives a single short packet event
1945 * by setting the CHAIN bit in the LINK field. In
1946 * addition some XHCI controllers have problems
1947 * sending a ZLP unless the CHAIN-BIT is set in
1948 * the LINK TRB.
1949 */
1950 XHCI_TRB_3_CHAIN_BIT;
1951
1952 td->td_trb[x].dwTrb3 = htole32(dword);
1953
1954 td->alt_next = td_alt_next;
1955 #ifdef USB_DEBUG
1956 xhci_dump_trb(&td->td_trb[x]);
1957 #endif
1958 usb_pc_cpu_flush(td->page_cache);
1959 }
1960
1961 if (precompute) {
1962 precompute = 0;
1963
1964 /* set up alt next pointer, if any */
1965 if (temp->last_frame) {
1966 td_alt_next = NULL;
1967 } else {
1968 /* we use this field internally */
1969 td_alt_next = td_next;
1970 }
1971
1972 /* restore */
1973 temp->shortpkt = shortpkt_old;
1974 temp->len = len_old;
1975 goto restart;
1976 }
1977
1978 /*
1979 * Remove cycle bit from the first TRB if we are
1980 * stepping them:
1981 */
1982 if (temp->step_td != 0) {
1983 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1984 usb_pc_cpu_flush(td_first->page_cache);
1985 }
1986
1987 /* clear TD SIZE to zero, hence this is the last TRB */
1988 /* remove chain bit because this is the last data TRB in the chain */
1989 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1990 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1991 /* remove CHAIN-BIT from last LINK TRB */
1992 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1993
1994 usb_pc_cpu_flush(td->page_cache);
1995
1996 temp->td = td;
1997 temp->td_next = td_next;
1998 }
1999
2000 static void
xhci_setup_generic_chain(struct usb_xfer * xfer)2001 xhci_setup_generic_chain(struct usb_xfer *xfer)
2002 {
2003 struct xhci_std_temp temp;
2004 struct xhci_td *td;
2005 uint32_t x;
2006 uint32_t y;
2007 uint8_t mult;
2008
2009 temp.do_isoc_sync = 0;
2010 temp.step_td = 0;
2011 temp.tbc = 0;
2012 temp.tlbpc = 0;
2013 temp.average = xfer->max_hc_frame_size;
2014 temp.max_packet_size = xfer->max_packet_size;
2015 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2016 temp.pc = NULL;
2017 temp.last_frame = 0;
2018 temp.offset = 0;
2019 temp.multishort = xfer->flags_int.isochronous_xfr ||
2020 xfer->flags_int.control_xfr ||
2021 xfer->flags_int.short_frames_ok;
2022
2023 /* toggle the DMA set we are using */
2024 xfer->flags_int.curr_dma_set ^= 1;
2025
2026 /* get next DMA set */
2027 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2028
2029 temp.td = NULL;
2030 temp.td_next = td;
2031
2032 xfer->td_transfer_first = td;
2033 xfer->td_transfer_cache = td;
2034
2035 if (xfer->flags_int.isochronous_xfr) {
2036 uint8_t shift;
2037
2038 /* compute multiplier for ISOCHRONOUS transfers */
2039 mult = xfer->endpoint->ecomp ?
2040 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2041 : 0;
2042 /* check for USB 2.0 multiplier */
2043 if (mult == 0) {
2044 mult = (xfer->endpoint->edesc->
2045 wMaxPacketSize[1] >> 3) & 3;
2046 }
2047 /* range check */
2048 if (mult > 2)
2049 mult = 3;
2050 else
2051 mult++;
2052
2053 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2054
2055 DPRINTF("MFINDEX=0x%08x\n", x);
2056
2057 switch (usbd_get_speed(xfer->xroot->udev)) {
2058 case USB_SPEED_FULL:
2059 shift = 3;
2060 temp.isoc_delta = 8; /* 1ms */
2061 x += temp.isoc_delta - 1;
2062 x &= ~(temp.isoc_delta - 1);
2063 break;
2064 default:
2065 shift = usbd_xfer_get_fps_shift(xfer);
2066 temp.isoc_delta = 1U << shift;
2067 x += temp.isoc_delta - 1;
2068 x &= ~(temp.isoc_delta - 1);
2069 /* simple frame load balancing */
2070 x += xfer->endpoint->usb_uframe;
2071 break;
2072 }
2073
2074 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2075
2076 if ((xfer->endpoint->is_synced == 0) ||
2077 (y < (xfer->nframes << shift)) ||
2078 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2079 /*
2080 * If there is data underflow or the pipe
2081 * queue is empty we schedule the transfer a
2082 * few frames ahead of the current frame
2083 * position. Else two isochronous transfers
2084 * might overlap.
2085 */
2086 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2087 xfer->endpoint->is_synced = 1;
2088 temp.do_isoc_sync = 1;
2089
2090 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2091 }
2092
2093 /* compute isochronous completion time */
2094
2095 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2096
2097 xfer->isoc_time_complete =
2098 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2099 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2100
2101 x = 0;
2102 temp.isoc_frame = xfer->endpoint->isoc_next;
2103 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2104
2105 xfer->endpoint->isoc_next += xfer->nframes << shift;
2106
2107 } else if (xfer->flags_int.control_xfr) {
2108
2109 /* check if we should prepend a setup message */
2110
2111 if (xfer->flags_int.control_hdr) {
2112
2113 temp.len = xfer->frlengths[0];
2114 temp.pc = xfer->frbuffers + 0;
2115 temp.shortpkt = temp.len ? 1 : 0;
2116 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2117 temp.direction = 0;
2118
2119 /* check for last frame */
2120 if (xfer->nframes == 1) {
2121 /* no STATUS stage yet, SETUP is last */
2122 if (xfer->flags_int.control_act)
2123 temp.last_frame = 1;
2124 }
2125
2126 xhci_setup_generic_chain_sub(&temp);
2127 }
2128 x = 1;
2129 mult = 1;
2130 temp.isoc_delta = 0;
2131 temp.isoc_frame = 0;
2132 temp.trb_type = xfer->flags_int.control_did_data ?
2133 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2134 } else {
2135 x = 0;
2136 mult = 1;
2137 temp.isoc_delta = 0;
2138 temp.isoc_frame = 0;
2139 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2140 }
2141
2142 if (x != xfer->nframes) {
2143 /* set up page_cache pointer */
2144 temp.pc = xfer->frbuffers + x;
2145 /* set endpoint direction */
2146 temp.direction = UE_GET_DIR(xfer->endpointno);
2147 }
2148
2149 while (x != xfer->nframes) {
2150
2151 /* DATA0 / DATA1 message */
2152
2153 temp.len = xfer->frlengths[x];
2154 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2155 x != 0 && temp.multishort == 0);
2156
2157 x++;
2158
2159 if (x == xfer->nframes) {
2160 if (xfer->flags_int.control_xfr) {
2161 /* no STATUS stage yet, DATA is last */
2162 if (xfer->flags_int.control_act)
2163 temp.last_frame = 1;
2164 } else {
2165 temp.last_frame = 1;
2166 }
2167 }
2168 if (temp.len == 0) {
2169
2170 /* make sure that we send an USB packet */
2171
2172 temp.shortpkt = 0;
2173
2174 temp.tbc = 0;
2175 temp.tlbpc = mult - 1;
2176
2177 } else if (xfer->flags_int.isochronous_xfr) {
2178
2179 uint8_t tdpc;
2180
2181 /*
2182 * Isochronous transfers don't have short
2183 * packet termination:
2184 */
2185
2186 temp.shortpkt = 1;
2187
2188 /* isochronous transfers have a transfer limit */
2189
2190 if (temp.len > xfer->max_frame_size)
2191 temp.len = xfer->max_frame_size;
2192
2193 /* compute TD packet count */
2194 tdpc = (temp.len + xfer->max_packet_size - 1) /
2195 xfer->max_packet_size;
2196
2197 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2198 temp.tlbpc = (tdpc % mult);
2199
2200 if (temp.tlbpc == 0)
2201 temp.tlbpc = mult - 1;
2202 else
2203 temp.tlbpc--;
2204 } else {
2205
2206 /* regular data transfer */
2207
2208 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2209 }
2210
2211 xhci_setup_generic_chain_sub(&temp);
2212
2213 if (xfer->flags_int.isochronous_xfr) {
2214 temp.offset += xfer->frlengths[x - 1];
2215 temp.isoc_frame += temp.isoc_delta;
2216 } else {
2217 /* get next Page Cache pointer */
2218 temp.pc = xfer->frbuffers + x;
2219 }
2220 }
2221
2222 /* check if we should append a status stage */
2223
2224 if (xfer->flags_int.control_xfr &&
2225 !xfer->flags_int.control_act) {
2226
2227 /*
2228 * Send a DATA1 message and invert the current
2229 * endpoint direction.
2230 */
2231 temp.step_td = (xfer->nframes != 0);
2232 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2233 temp.len = 0;
2234 temp.pc = NULL;
2235 temp.shortpkt = 0;
2236 temp.last_frame = 1;
2237 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2238
2239 xhci_setup_generic_chain_sub(&temp);
2240 }
2241
2242 td = temp.td;
2243
2244 /* must have at least one frame! */
2245
2246 xfer->td_transfer_last = td;
2247
2248 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2249 }
2250
2251 static void
xhci_set_slot_pointer(struct xhci_softc * sc,uint8_t index,uint64_t dev_addr)2252 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2253 {
2254 struct usb_page_search buf_res;
2255 struct xhci_dev_ctx_addr *pdctxa;
2256
2257 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2258
2259 pdctxa = buf_res.buffer;
2260
2261 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2262
2263 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2264
2265 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2266 }
2267
2268 static usb_error_t
xhci_configure_mask(struct usb_device * udev,uint32_t mask,uint8_t drop)2269 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2270 {
2271 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2272 struct usb_page_search buf_inp;
2273 struct xhci_input_dev_ctx *pinp;
2274 uint32_t temp;
2275 uint8_t index;
2276 uint8_t x;
2277
2278 index = udev->controller_slot_id;
2279
2280 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2281
2282 pinp = buf_inp.buffer;
2283
2284 if (drop) {
2285 mask &= XHCI_INCTX_NON_CTRL_MASK;
2286 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2287 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2288 } else {
2289 /*
2290 * Some hardware requires that we drop the endpoint
2291 * context before adding it again:
2292 */
2293 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2294 mask & XHCI_INCTX_NON_CTRL_MASK);
2295
2296 /* Add new endpoint context */
2297 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2298
2299 /* find most significant set bit */
2300 for (x = 31; x != 1; x--) {
2301 if (mask & (1 << x))
2302 break;
2303 }
2304
2305 /* adjust */
2306 x--;
2307
2308 /* figure out the maximum number of contexts */
2309 if (x > sc->sc_hw.devs[index].context_num)
2310 sc->sc_hw.devs[index].context_num = x;
2311 else
2312 x = sc->sc_hw.devs[index].context_num;
2313
2314 /* update number of contexts */
2315 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2316 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2317 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2318 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2319 }
2320 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2321 return (0);
2322 }
2323
2324 static usb_error_t
xhci_configure_endpoint(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct xhci_endpoint_ext * pepext,uint16_t interval,uint8_t max_packet_count,uint8_t mult,uint8_t fps_shift,uint16_t max_packet_size,uint16_t max_frame_size,uint8_t ep_mode)2325 xhci_configure_endpoint(struct usb_device *udev,
2326 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2327 uint16_t interval, uint8_t max_packet_count,
2328 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2329 uint16_t max_frame_size, uint8_t ep_mode)
2330 {
2331 struct usb_page_search buf_inp;
2332 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2333 struct xhci_input_dev_ctx *pinp;
2334 uint64_t ring_addr = pepext->physaddr;
2335 uint32_t temp;
2336 uint8_t index;
2337 uint8_t epno;
2338 uint8_t type;
2339
2340 index = udev->controller_slot_id;
2341
2342 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2343
2344 pinp = buf_inp.buffer;
2345
2346 epno = edesc->bEndpointAddress;
2347 type = edesc->bmAttributes & UE_XFERTYPE;
2348
2349 if (type == UE_CONTROL)
2350 epno |= UE_DIR_IN;
2351
2352 epno = XHCI_EPNO2EPID(epno);
2353
2354 if (epno == 0)
2355 return (USB_ERR_NO_PIPE); /* invalid */
2356
2357 if (max_packet_count == 0)
2358 return (USB_ERR_BAD_BUFSIZE);
2359
2360 max_packet_count--;
2361
2362 if (mult == 0)
2363 return (USB_ERR_BAD_BUFSIZE);
2364
2365 /* store endpoint mode */
2366 pepext->trb_ep_mode = ep_mode;
2367 /* store bMaxPacketSize for control endpoints */
2368 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2369 usb_pc_cpu_flush(pepext->page_cache);
2370
2371 if (ep_mode == USB_EP_MODE_STREAMS) {
2372 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2373 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2374 XHCI_EPCTX_0_LSA_SET(1);
2375
2376 ring_addr += sizeof(struct xhci_trb) *
2377 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2378 } else {
2379 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2380 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2381 XHCI_EPCTX_0_LSA_SET(0);
2382
2383 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2384 }
2385
2386 switch (udev->speed) {
2387 case USB_SPEED_FULL:
2388 case USB_SPEED_LOW:
2389 /* 1ms -> 125us */
2390 fps_shift += 3;
2391 break;
2392 default:
2393 break;
2394 }
2395
2396 switch (type) {
2397 case UE_INTERRUPT:
2398 if (fps_shift > 3)
2399 fps_shift--;
2400 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2401 break;
2402 case UE_ISOCHRONOUS:
2403 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2404
2405 switch (udev->speed) {
2406 case USB_SPEED_SUPER:
2407 if (mult > 3)
2408 mult = 3;
2409 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2410 max_packet_count /= mult;
2411 break;
2412 default:
2413 break;
2414 }
2415 break;
2416 default:
2417 break;
2418 }
2419
2420 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2421
2422 temp =
2423 XHCI_EPCTX_1_HID_SET(0) |
2424 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2425 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2426
2427 /*
2428 * Always enable the "three strikes and you are gone" feature
2429 * except for ISOCHRONOUS endpoints. This is suggested by
2430 * section 4.3.3 in the XHCI specification about device slot
2431 * initialisation.
2432 */
2433 if (type != UE_ISOCHRONOUS)
2434 temp |= XHCI_EPCTX_1_CERR_SET(3);
2435
2436 switch (type) {
2437 case UE_CONTROL:
2438 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2439 break;
2440 case UE_ISOCHRONOUS:
2441 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2442 break;
2443 case UE_BULK:
2444 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2445 break;
2446 default:
2447 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2448 break;
2449 }
2450
2451 /* check for IN direction */
2452 if (epno & 1)
2453 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2454
2455 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2456 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2457
2458 switch (edesc->bmAttributes & UE_XFERTYPE) {
2459 case UE_INTERRUPT:
2460 case UE_ISOCHRONOUS:
2461 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2462 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2463 max_frame_size));
2464 break;
2465 case UE_CONTROL:
2466 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2467 break;
2468 default:
2469 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2470 break;
2471 }
2472
2473 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2474
2475 #ifdef USB_DEBUG
2476 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2477 #endif
2478 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2479
2480 return (0); /* success */
2481 }
2482
2483 static usb_error_t
xhci_configure_endpoint_by_xfer(struct usb_xfer * xfer)2484 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2485 {
2486 struct xhci_endpoint_ext *pepext;
2487 struct usb_endpoint_ss_comp_descriptor *ecomp;
2488 usb_stream_t x;
2489
2490 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2491 xfer->endpoint->edesc);
2492
2493 ecomp = xfer->endpoint->ecomp;
2494
2495 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2496 uint64_t temp;
2497
2498 /* halt any transfers */
2499 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2500
2501 /* compute start of TRB ring for stream "x" */
2502 temp = pepext->physaddr +
2503 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2504 XHCI_SCTX_0_SCT_SEC_TR_RING;
2505
2506 /* make tree structure */
2507 pepext->trb[(XHCI_MAX_TRANSFERS *
2508 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2509
2510 /* reserved fields */
2511 pepext->trb[(XHCI_MAX_TRANSFERS *
2512 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2513 pepext->trb[(XHCI_MAX_TRANSFERS *
2514 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2515 }
2516 usb_pc_cpu_flush(pepext->page_cache);
2517
2518 return (xhci_configure_endpoint(xfer->xroot->udev,
2519 xfer->endpoint->edesc, pepext,
2520 xfer->interval, xfer->max_packet_count,
2521 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2522 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2523 xfer->max_frame_size, xfer->endpoint->ep_mode));
2524 }
2525
2526 static usb_error_t
xhci_configure_device(struct usb_device * udev)2527 xhci_configure_device(struct usb_device *udev)
2528 {
2529 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2530 struct usb_page_search buf_inp;
2531 struct usb_page_cache *pcinp;
2532 struct xhci_input_dev_ctx *pinp;
2533 struct usb_device *hubdev;
2534 uint32_t temp;
2535 uint32_t route;
2536 uint32_t rh_port;
2537 uint8_t is_hub;
2538 uint8_t index;
2539 uint8_t depth;
2540
2541 index = udev->controller_slot_id;
2542
2543 DPRINTF("index=%u\n", index);
2544
2545 pcinp = &sc->sc_hw.devs[index].input_pc;
2546
2547 usbd_get_page(pcinp, 0, &buf_inp);
2548
2549 pinp = buf_inp.buffer;
2550
2551 rh_port = 0;
2552 route = 0;
2553
2554 /* figure out route string and root HUB port number */
2555
2556 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2557
2558 if (hubdev->parent_hub == NULL)
2559 break;
2560
2561 depth = hubdev->parent_hub->depth;
2562
2563 /*
2564 * NOTE: HS/FS/LS devices and the SS root HUB can have
2565 * more than 15 ports
2566 */
2567
2568 rh_port = hubdev->port_no;
2569
2570 if (depth == 0)
2571 break;
2572
2573 if (rh_port > 15)
2574 rh_port = 15;
2575
2576 if (depth < 6)
2577 route |= rh_port << (4 * (depth - 1));
2578 }
2579
2580 DPRINTF("Route=0x%08x\n", route);
2581
2582 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2583 XHCI_SCTX_0_CTX_NUM_SET(
2584 sc->sc_hw.devs[index].context_num + 1);
2585
2586 switch (udev->speed) {
2587 case USB_SPEED_LOW:
2588 temp |= XHCI_SCTX_0_SPEED_SET(2);
2589 if (udev->parent_hs_hub != NULL &&
2590 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2591 UDPROTO_HSHUBMTT) {
2592 DPRINTF("Device inherits MTT\n");
2593 temp |= XHCI_SCTX_0_MTT_SET(1);
2594 }
2595 break;
2596 case USB_SPEED_HIGH:
2597 temp |= XHCI_SCTX_0_SPEED_SET(3);
2598 if (sc->sc_hw.devs[index].nports != 0 &&
2599 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2600 DPRINTF("HUB supports MTT\n");
2601 temp |= XHCI_SCTX_0_MTT_SET(1);
2602 }
2603 break;
2604 case USB_SPEED_FULL:
2605 temp |= XHCI_SCTX_0_SPEED_SET(1);
2606 if (udev->parent_hs_hub != NULL &&
2607 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2608 UDPROTO_HSHUBMTT) {
2609 DPRINTF("Device inherits MTT\n");
2610 temp |= XHCI_SCTX_0_MTT_SET(1);
2611 }
2612 break;
2613 default:
2614 temp |= XHCI_SCTX_0_SPEED_SET(4);
2615 break;
2616 }
2617
2618 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2619 (udev->speed == USB_SPEED_SUPER ||
2620 udev->speed == USB_SPEED_HIGH);
2621
2622 if (is_hub) {
2623 temp |= XHCI_SCTX_0_HUB_SET(1);
2624 }
2625
2626 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2627
2628 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2629
2630 if (is_hub) {
2631 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2632 sc->sc_hw.devs[index].nports);
2633 }
2634
2635 switch (udev->speed) {
2636 case USB_SPEED_SUPER:
2637 switch (sc->sc_hw.devs[index].state) {
2638 case XHCI_ST_ADDRESSED:
2639 case XHCI_ST_CONFIGURED:
2640 /* enable power save */
2641 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2642 break;
2643 default:
2644 /* disable power save */
2645 break;
2646 }
2647 break;
2648 default:
2649 break;
2650 }
2651
2652 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2653
2654 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2655
2656 if (is_hub) {
2657 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2658 sc->sc_hw.devs[index].tt);
2659 }
2660
2661 hubdev = udev->parent_hs_hub;
2662
2663 /* check if we should activate the transaction translator */
2664 switch (udev->speed) {
2665 case USB_SPEED_FULL:
2666 case USB_SPEED_LOW:
2667 if (hubdev != NULL) {
2668 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2669 hubdev->controller_slot_id);
2670 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2671 udev->hs_port_no);
2672 }
2673 break;
2674 default:
2675 break;
2676 }
2677
2678 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2679
2680 /*
2681 * These fields should be initialized to zero, according to
2682 * XHCI section 6.2.2 - slot context:
2683 */
2684 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2685 XHCI_SCTX_3_SLOT_STATE_SET(0);
2686
2687 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2688
2689 #ifdef USB_DEBUG
2690 xhci_dump_device(sc, &pinp->ctx_slot);
2691 #endif
2692 usb_pc_cpu_flush(pcinp);
2693
2694 return (0); /* success */
2695 }
2696
2697 static usb_error_t
xhci_alloc_device_ext(struct usb_device * udev)2698 xhci_alloc_device_ext(struct usb_device *udev)
2699 {
2700 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2701 struct usb_page_search buf_dev;
2702 struct usb_page_search buf_ep;
2703 struct xhci_trb *trb;
2704 struct usb_page_cache *pc;
2705 struct usb_page *pg;
2706 uint64_t addr;
2707 uint8_t index;
2708 uint8_t i;
2709
2710 index = udev->controller_slot_id;
2711
2712 pc = &sc->sc_hw.devs[index].device_pc;
2713 pg = &sc->sc_hw.devs[index].device_pg;
2714
2715 /* need to initialize the page cache */
2716 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2717
2718 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2719 (2 * sizeof(struct xhci_dev_ctx)) :
2720 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2721 goto error;
2722
2723 usbd_get_page(pc, 0, &buf_dev);
2724
2725 pc = &sc->sc_hw.devs[index].input_pc;
2726 pg = &sc->sc_hw.devs[index].input_pg;
2727
2728 /* need to initialize the page cache */
2729 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2730
2731 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2732 (2 * sizeof(struct xhci_input_dev_ctx)) :
2733 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2734 goto error;
2735 }
2736
2737 /* initialize all endpoint LINK TRBs */
2738
2739 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2740
2741 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2742 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2743
2744 /* need to initialize the page cache */
2745 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2746
2747 if (usb_pc_alloc_mem(pc, pg,
2748 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2749 goto error;
2750 }
2751
2752 /* lookup endpoint TRB ring */
2753 usbd_get_page(pc, 0, &buf_ep);
2754
2755 /* get TRB pointer */
2756 trb = buf_ep.buffer;
2757 trb += XHCI_MAX_TRANSFERS - 1;
2758
2759 /* get TRB start address */
2760 addr = buf_ep.physaddr;
2761
2762 /* create LINK TRB */
2763 trb->qwTrb0 = htole64(addr);
2764 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2765 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2766 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2767
2768 usb_pc_cpu_flush(pc);
2769 }
2770
2771 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2772
2773 return (0);
2774
2775 error:
2776 xhci_free_device_ext(udev);
2777
2778 return (USB_ERR_NOMEM);
2779 }
2780
2781 static void
xhci_free_device_ext(struct usb_device * udev)2782 xhci_free_device_ext(struct usb_device *udev)
2783 {
2784 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2785 uint8_t index;
2786 uint8_t i;
2787
2788 index = udev->controller_slot_id;
2789 xhci_set_slot_pointer(sc, index, 0);
2790
2791 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2792 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2793 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2794 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2795 }
2796
2797 static struct xhci_endpoint_ext *
xhci_get_endpoint_ext(struct usb_device * udev,struct usb_endpoint_descriptor * edesc)2798 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2799 {
2800 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2801 struct xhci_endpoint_ext *pepext;
2802 struct usb_page_cache *pc;
2803 struct usb_page_search buf_ep;
2804 uint8_t epno;
2805 uint8_t index;
2806
2807 epno = edesc->bEndpointAddress;
2808 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2809 epno |= UE_DIR_IN;
2810
2811 epno = XHCI_EPNO2EPID(epno);
2812
2813 index = udev->controller_slot_id;
2814
2815 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2816
2817 usbd_get_page(pc, 0, &buf_ep);
2818
2819 pepext = &sc->sc_hw.devs[index].endp[epno];
2820 pepext->page_cache = pc;
2821 pepext->trb = buf_ep.buffer;
2822 pepext->physaddr = buf_ep.physaddr;
2823
2824 return (pepext);
2825 }
2826
2827 static void
xhci_endpoint_doorbell(struct usb_xfer * xfer)2828 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2829 {
2830 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2831 uint8_t epno;
2832 uint8_t index;
2833
2834 epno = xfer->endpointno;
2835 if (xfer->flags_int.control_xfr)
2836 epno |= UE_DIR_IN;
2837
2838 epno = XHCI_EPNO2EPID(epno);
2839 index = xfer->xroot->udev->controller_slot_id;
2840
2841 if (xfer->xroot->udev->flags.self_suspended == 0) {
2842 XWRITE4(sc, door, XHCI_DOORBELL(index),
2843 epno | XHCI_DB_SID_SET(xfer->stream_id));
2844 }
2845 }
2846
2847 static void
xhci_transfer_remove(struct usb_xfer * xfer,usb_error_t error)2848 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2849 {
2850 struct xhci_endpoint_ext *pepext;
2851
2852 if (xfer->flags_int.bandwidth_reclaimed) {
2853 xfer->flags_int.bandwidth_reclaimed = 0;
2854
2855 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2856 xfer->endpoint->edesc);
2857
2858 pepext->trb_used[xfer->stream_id]--;
2859
2860 pepext->xfer[xfer->qh_pos] = NULL;
2861
2862 if (error && pepext->trb_running != 0) {
2863 pepext->trb_halted = 1;
2864 pepext->trb_running = 0;
2865 }
2866 }
2867 }
2868
2869 static usb_error_t
xhci_transfer_insert(struct usb_xfer * xfer)2870 xhci_transfer_insert(struct usb_xfer *xfer)
2871 {
2872 struct xhci_td *td_first;
2873 struct xhci_td *td_last;
2874 struct xhci_trb *trb_link;
2875 struct xhci_endpoint_ext *pepext;
2876 uint64_t addr;
2877 usb_stream_t id;
2878 uint8_t i;
2879 uint8_t inext;
2880 uint8_t trb_limit;
2881
2882 DPRINTFN(8, "\n");
2883
2884 id = xfer->stream_id;
2885
2886 /* check if already inserted */
2887 if (xfer->flags_int.bandwidth_reclaimed) {
2888 DPRINTFN(8, "Already in schedule\n");
2889 return (0);
2890 }
2891
2892 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2893 xfer->endpoint->edesc);
2894
2895 td_first = xfer->td_transfer_first;
2896 td_last = xfer->td_transfer_last;
2897 addr = pepext->physaddr;
2898
2899 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2900 case UE_CONTROL:
2901 case UE_INTERRUPT:
2902 /* single buffered */
2903 trb_limit = 1;
2904 break;
2905 default:
2906 /* multi buffered */
2907 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2908 break;
2909 }
2910
2911 if (pepext->trb_used[id] >= trb_limit) {
2912 DPRINTFN(8, "Too many TDs queued.\n");
2913 return (USB_ERR_NOMEM);
2914 }
2915
2916 /* check if bMaxPacketSize changed */
2917 if (xfer->flags_int.control_xfr != 0 &&
2918 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2919
2920 DPRINTFN(8, "Reconfigure control endpoint\n");
2921
2922 /* force driver to reconfigure endpoint */
2923 pepext->trb_halted = 1;
2924 pepext->trb_running = 0;
2925 }
2926
2927 /* check for stopped condition, after putting transfer on interrupt queue */
2928 if (pepext->trb_running == 0) {
2929 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2930
2931 DPRINTFN(8, "Not running\n");
2932
2933 /* start configuration */
2934 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2935 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2936 return (0);
2937 }
2938
2939 pepext->trb_used[id]++;
2940
2941 /* get current TRB index */
2942 i = pepext->trb_index[id];
2943
2944 /* get next TRB index */
2945 inext = (i + 1);
2946
2947 /* the last entry of the ring is a hardcoded link TRB */
2948 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2949 inext = 0;
2950
2951 /* store next TRB index, before stream ID offset is added */
2952 pepext->trb_index[id] = inext;
2953
2954 /* offset for stream */
2955 i += id * XHCI_MAX_TRANSFERS;
2956 inext += id * XHCI_MAX_TRANSFERS;
2957
2958 /* compute terminating return address */
2959 addr += (inext * sizeof(struct xhci_trb));
2960
2961 /* compute link TRB pointer */
2962 trb_link = td_last->td_trb + td_last->ntrb;
2963
2964 /* update next pointer of last link TRB */
2965 trb_link->qwTrb0 = htole64(addr);
2966 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2967 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2968 XHCI_TRB_3_CYCLE_BIT |
2969 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2970
2971 #ifdef USB_DEBUG
2972 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2973 #endif
2974 usb_pc_cpu_flush(td_last->page_cache);
2975
2976 /* write ahead chain end marker */
2977
2978 pepext->trb[inext].qwTrb0 = 0;
2979 pepext->trb[inext].dwTrb2 = 0;
2980 pepext->trb[inext].dwTrb3 = 0;
2981
2982 /* update next pointer of link TRB */
2983
2984 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2985 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2986
2987 #ifdef USB_DEBUG
2988 xhci_dump_trb(&pepext->trb[i]);
2989 #endif
2990 usb_pc_cpu_flush(pepext->page_cache);
2991
2992 /* toggle cycle bit which activates the transfer chain */
2993
2994 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2995 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2996
2997 usb_pc_cpu_flush(pepext->page_cache);
2998
2999 DPRINTF("qh_pos = %u\n", i);
3000
3001 pepext->xfer[i] = xfer;
3002
3003 xfer->qh_pos = i;
3004
3005 xfer->flags_int.bandwidth_reclaimed = 1;
3006
3007 xhci_endpoint_doorbell(xfer);
3008
3009 return (0);
3010 }
3011
3012 static void
xhci_root_intr(struct xhci_softc * sc)3013 xhci_root_intr(struct xhci_softc *sc)
3014 {
3015 uint16_t i;
3016
3017 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
3018
3019 /* clear any old interrupt data */
3020 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3021
3022 for (i = 1; i <= sc->sc_noport; i++) {
3023 /* pick out CHANGE bits from the status register */
3024 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3025 XHCI_PS_CSC | XHCI_PS_PEC |
3026 XHCI_PS_OCC | XHCI_PS_WRC |
3027 XHCI_PS_PRC | XHCI_PS_PLC |
3028 XHCI_PS_CEC)) {
3029 setbit(sc->sc_hub_idata, i);
3030 DPRINTF("port %d changed\n", i);
3031 }
3032 }
3033 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3034 sizeof(sc->sc_hub_idata));
3035 }
3036
3037 /*------------------------------------------------------------------------*
3038 * xhci_device_done - XHCI done handler
3039 *
3040 * NOTE: This function can be called two times in a row on
3041 * the same USB transfer. From close and from interrupt.
3042 *------------------------------------------------------------------------*/
3043 static void
xhci_device_done(struct usb_xfer * xfer,usb_error_t error)3044 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3045 {
3046 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3047 xfer, xfer->endpoint, error);
3048
3049 /* remove transfer from HW queue */
3050 xhci_transfer_remove(xfer, error);
3051
3052 /* dequeue transfer and start next transfer */
3053 usbd_transfer_done(xfer, error);
3054 }
3055
3056 /*------------------------------------------------------------------------*
3057 * XHCI data transfer support (generic type)
3058 *------------------------------------------------------------------------*/
3059 static void
xhci_device_generic_open(struct usb_xfer * xfer)3060 xhci_device_generic_open(struct usb_xfer *xfer)
3061 {
3062 if (xfer->flags_int.isochronous_xfr) {
3063 switch (xfer->xroot->udev->speed) {
3064 case USB_SPEED_FULL:
3065 break;
3066 default:
3067 usb_hs_bandwidth_alloc(xfer);
3068 break;
3069 }
3070 }
3071 }
3072
3073 static void
xhci_device_generic_close(struct usb_xfer * xfer)3074 xhci_device_generic_close(struct usb_xfer *xfer)
3075 {
3076 DPRINTF("\n");
3077
3078 xhci_device_done(xfer, USB_ERR_CANCELLED);
3079
3080 if (xfer->flags_int.isochronous_xfr) {
3081 switch (xfer->xroot->udev->speed) {
3082 case USB_SPEED_FULL:
3083 break;
3084 default:
3085 usb_hs_bandwidth_free(xfer);
3086 break;
3087 }
3088 }
3089 }
3090
3091 static void
xhci_device_generic_multi_enter(struct usb_endpoint * ep,usb_stream_t stream_id,struct usb_xfer * enter_xfer)3092 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3093 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3094 {
3095 struct usb_xfer *xfer;
3096
3097 /* check if there is a current transfer */
3098 xfer = ep->endpoint_q[stream_id].curr;
3099 if (xfer == NULL)
3100 return;
3101
3102 /*
3103 * Check if the current transfer is started and then pickup
3104 * the next one, if any. Else wait for next start event due to
3105 * block on failure feature.
3106 */
3107 if (!xfer->flags_int.bandwidth_reclaimed)
3108 return;
3109
3110 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3111 if (xfer == NULL) {
3112 /*
3113 * In case of enter we have to consider that the
3114 * transfer is queued by the USB core after the enter
3115 * method is called.
3116 */
3117 xfer = enter_xfer;
3118
3119 if (xfer == NULL)
3120 return;
3121 }
3122
3123 /* try to multi buffer */
3124 xhci_transfer_insert(xfer);
3125 }
3126
3127 static void
xhci_device_generic_enter(struct usb_xfer * xfer)3128 xhci_device_generic_enter(struct usb_xfer *xfer)
3129 {
3130 DPRINTF("\n");
3131
3132 /* set up TD's and QH */
3133 xhci_setup_generic_chain(xfer);
3134
3135 xhci_device_generic_multi_enter(xfer->endpoint,
3136 xfer->stream_id, xfer);
3137 }
3138
3139 static void
xhci_device_generic_start(struct usb_xfer * xfer)3140 xhci_device_generic_start(struct usb_xfer *xfer)
3141 {
3142 DPRINTF("\n");
3143
3144 /* try to insert xfer on HW queue */
3145 xhci_transfer_insert(xfer);
3146
3147 /* try to multi buffer */
3148 xhci_device_generic_multi_enter(xfer->endpoint,
3149 xfer->stream_id, NULL);
3150
3151 /* add transfer last on interrupt queue */
3152 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3153
3154 /* start timeout, if any */
3155 if (xfer->timeout != 0)
3156 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3157 }
3158
3159 static const struct usb_pipe_methods xhci_device_generic_methods =
3160 {
3161 .open = xhci_device_generic_open,
3162 .close = xhci_device_generic_close,
3163 .enter = xhci_device_generic_enter,
3164 .start = xhci_device_generic_start,
3165 };
3166
3167 /*------------------------------------------------------------------------*
3168 * xhci root HUB support
3169 *------------------------------------------------------------------------*
3170 * Simulate a hardware HUB by handling all the necessary requests.
3171 *------------------------------------------------------------------------*/
3172
3173 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3174
3175 static const
3176 struct usb_device_descriptor xhci_devd =
3177 {
3178 .bLength = sizeof(xhci_devd),
3179 .bDescriptorType = UDESC_DEVICE, /* type */
3180 HSETW(.bcdUSB, 0x0300), /* USB version */
3181 .bDeviceClass = UDCLASS_HUB, /* class */
3182 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3183 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3184 .bMaxPacketSize = 9, /* max packet size */
3185 HSETW(.idVendor, 0x0000), /* vendor */
3186 HSETW(.idProduct, 0x0000), /* product */
3187 HSETW(.bcdDevice, 0x0100), /* device version */
3188 .iManufacturer = 1,
3189 .iProduct = 2,
3190 .iSerialNumber = 0,
3191 .bNumConfigurations = 1, /* # of configurations */
3192 };
3193
3194 static const
3195 struct xhci_bos_desc xhci_bosd = {
3196 .bosd = {
3197 .bLength = sizeof(xhci_bosd.bosd),
3198 .bDescriptorType = UDESC_BOS,
3199 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3200 .bNumDeviceCaps = 3,
3201 },
3202 .usb2extd = {
3203 .bLength = sizeof(xhci_bosd.usb2extd),
3204 .bDescriptorType = 1,
3205 .bDevCapabilityType = 2,
3206 .bmAttributes[0] = 2,
3207 },
3208 .usbdcd = {
3209 .bLength = sizeof(xhci_bosd.usbdcd),
3210 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3211 .bDevCapabilityType = 3,
3212 .bmAttributes = 0, /* XXX */
3213 HSETW(.wSpeedsSupported, 0x000C),
3214 .bFunctionalitySupport = 8,
3215 .bU1DevExitLat = 255, /* dummy - not used */
3216 .wU2DevExitLat = { 0x00, 0x08 },
3217 },
3218 .cidd = {
3219 .bLength = sizeof(xhci_bosd.cidd),
3220 .bDescriptorType = 1,
3221 .bDevCapabilityType = 4,
3222 .bReserved = 0,
3223 .bContainerID = 0, /* XXX */
3224 },
3225 };
3226
3227 static const
3228 struct xhci_config_desc xhci_confd = {
3229 .confd = {
3230 .bLength = sizeof(xhci_confd.confd),
3231 .bDescriptorType = UDESC_CONFIG,
3232 .wTotalLength[0] = sizeof(xhci_confd),
3233 .bNumInterface = 1,
3234 .bConfigurationValue = 1,
3235 .iConfiguration = 0,
3236 .bmAttributes = UC_SELF_POWERED,
3237 .bMaxPower = 0 /* max power */
3238 },
3239 .ifcd = {
3240 .bLength = sizeof(xhci_confd.ifcd),
3241 .bDescriptorType = UDESC_INTERFACE,
3242 .bNumEndpoints = 1,
3243 .bInterfaceClass = UICLASS_HUB,
3244 .bInterfaceSubClass = UISUBCLASS_HUB,
3245 .bInterfaceProtocol = 0,
3246 },
3247 .endpd = {
3248 .bLength = sizeof(xhci_confd.endpd),
3249 .bDescriptorType = UDESC_ENDPOINT,
3250 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3251 .bmAttributes = UE_INTERRUPT,
3252 .wMaxPacketSize[0] = 2, /* max 15 ports */
3253 .bInterval = 255,
3254 },
3255 .endpcd = {
3256 .bLength = sizeof(xhci_confd.endpcd),
3257 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3258 .bMaxBurst = 0,
3259 .bmAttributes = 0,
3260 },
3261 };
3262
3263 static const
3264 struct usb_hub_ss_descriptor xhci_hubd = {
3265 .bLength = sizeof(xhci_hubd),
3266 .bDescriptorType = UDESC_SS_HUB,
3267 };
3268
3269 static usb_error_t
xhci_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)3270 xhci_roothub_exec(struct usb_device *udev,
3271 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3272 {
3273 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3274 const char *str_ptr;
3275 const void *ptr;
3276 uint32_t port;
3277 uint32_t v;
3278 uint16_t len;
3279 uint16_t i;
3280 uint16_t value;
3281 uint16_t index;
3282 uint8_t j;
3283 usb_error_t err;
3284
3285 USB_BUS_LOCK_ASSERT(&sc->sc_bus);
3286
3287 /* buffer reset */
3288 ptr = (const void *)&sc->sc_hub_desc;
3289 len = 0;
3290 err = 0;
3291
3292 value = UGETW(req->wValue);
3293 index = UGETW(req->wIndex);
3294
3295 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3296 "wValue=0x%04x wIndex=0x%04x\n",
3297 req->bmRequestType, req->bRequest,
3298 UGETW(req->wLength), value, index);
3299
3300 #define C(x,y) ((x) | ((y) << 8))
3301 switch (C(req->bRequest, req->bmRequestType)) {
3302 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3303 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3304 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3305 /*
3306 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3307 * for the integrated root hub.
3308 */
3309 break;
3310 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3311 len = 1;
3312 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3313 break;
3314 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3315 switch (value >> 8) {
3316 case UDESC_DEVICE:
3317 if ((value & 0xff) != 0) {
3318 err = USB_ERR_IOERROR;
3319 goto done;
3320 }
3321 len = sizeof(xhci_devd);
3322 ptr = (const void *)&xhci_devd;
3323 break;
3324
3325 case UDESC_BOS:
3326 if ((value & 0xff) != 0) {
3327 err = USB_ERR_IOERROR;
3328 goto done;
3329 }
3330 len = sizeof(xhci_bosd);
3331 ptr = (const void *)&xhci_bosd;
3332 break;
3333
3334 case UDESC_CONFIG:
3335 if ((value & 0xff) != 0) {
3336 err = USB_ERR_IOERROR;
3337 goto done;
3338 }
3339 len = sizeof(xhci_confd);
3340 ptr = (const void *)&xhci_confd;
3341 break;
3342
3343 case UDESC_STRING:
3344 switch (value & 0xff) {
3345 case 0: /* Language table */
3346 str_ptr = "\001";
3347 break;
3348
3349 case 1: /* Vendor */
3350 str_ptr = sc->sc_vendor;
3351 break;
3352
3353 case 2: /* Product */
3354 str_ptr = "XHCI root HUB";
3355 break;
3356
3357 default:
3358 str_ptr = "";
3359 break;
3360 }
3361
3362 len = usb_make_str_desc(
3363 sc->sc_hub_desc.temp,
3364 sizeof(sc->sc_hub_desc.temp),
3365 str_ptr);
3366 break;
3367
3368 default:
3369 err = USB_ERR_IOERROR;
3370 goto done;
3371 }
3372 break;
3373 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3374 len = 1;
3375 sc->sc_hub_desc.temp[0] = 0;
3376 break;
3377 case C(UR_GET_STATUS, UT_READ_DEVICE):
3378 len = 2;
3379 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3380 break;
3381 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3382 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3383 len = 2;
3384 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3385 break;
3386 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3387 if (value >= XHCI_MAX_DEVICES) {
3388 err = USB_ERR_IOERROR;
3389 goto done;
3390 }
3391 break;
3392 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3393 if (value != 0 && value != 1) {
3394 err = USB_ERR_IOERROR;
3395 goto done;
3396 }
3397 sc->sc_conf = value;
3398 break;
3399 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3400 break;
3401 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3402 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3403 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3404 err = USB_ERR_IOERROR;
3405 goto done;
3406 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3407 break;
3408 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3409 break;
3410 /* Hub requests */
3411 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3412 break;
3413 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3414 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3415
3416 if ((index < 1) ||
3417 (index > sc->sc_noport)) {
3418 err = USB_ERR_IOERROR;
3419 goto done;
3420 }
3421 port = XHCI_PORTSC(index);
3422
3423 v = XREAD4(sc, oper, port);
3424 i = XHCI_PS_PLS_GET(v);
3425 v &= ~XHCI_PS_CLEAR;
3426
3427 switch (value) {
3428 case UHF_C_BH_PORT_RESET:
3429 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3430 break;
3431 case UHF_C_PORT_CONFIG_ERROR:
3432 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3433 break;
3434 case UHF_C_PORT_SUSPEND:
3435 case UHF_C_PORT_LINK_STATE:
3436 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3437 break;
3438 case UHF_C_PORT_CONNECTION:
3439 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3440 break;
3441 case UHF_C_PORT_ENABLE:
3442 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3443 break;
3444 case UHF_C_PORT_OVER_CURRENT:
3445 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3446 break;
3447 case UHF_C_PORT_RESET:
3448 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3449 break;
3450 case UHF_PORT_ENABLE:
3451 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3452 break;
3453 case UHF_PORT_POWER:
3454 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3455 break;
3456 case UHF_PORT_INDICATOR:
3457 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3458 break;
3459 case UHF_PORT_SUSPEND:
3460
3461 /* U3 -> U15 */
3462 if (i == 3) {
3463 XWRITE4(sc, oper, port, v |
3464 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3465 }
3466
3467 /* wait 20ms for resume sequence to complete */
3468 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50);
3469
3470 /* U0 */
3471 XWRITE4(sc, oper, port, v |
3472 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3473 break;
3474 default:
3475 err = USB_ERR_IOERROR;
3476 goto done;
3477 }
3478 break;
3479
3480 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3481 if ((value & 0xff) != 0) {
3482 err = USB_ERR_IOERROR;
3483 goto done;
3484 }
3485
3486 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3487
3488 sc->sc_hub_desc.hubd = xhci_hubd;
3489
3490 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3491
3492 if (XHCI_HCS0_PPC(v))
3493 i = UHD_PWR_INDIVIDUAL;
3494 else
3495 i = UHD_PWR_GANGED;
3496
3497 if (XHCI_HCS0_PIND(v))
3498 i |= UHD_PORT_IND;
3499
3500 i |= UHD_OC_INDIVIDUAL;
3501
3502 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3503
3504 /* see XHCI section 5.4.9: */
3505 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3506
3507 for (j = 1; j <= sc->sc_noport; j++) {
3508
3509 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3510 if (v & XHCI_PS_DR) {
3511 sc->sc_hub_desc.hubd.
3512 DeviceRemovable[j / 8] |= 1U << (j % 8);
3513 }
3514 }
3515 len = sc->sc_hub_desc.hubd.bLength;
3516 break;
3517
3518 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3519 len = 16;
3520 memset(sc->sc_hub_desc.temp, 0, 16);
3521 break;
3522
3523 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3524 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3525
3526 if ((index < 1) ||
3527 (index > sc->sc_noport)) {
3528 err = USB_ERR_IOERROR;
3529 goto done;
3530 }
3531
3532 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3533
3534 DPRINTFN(9, "port status=0x%08x\n", v);
3535
3536 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3537
3538 switch (XHCI_PS_SPEED_GET(v)) {
3539 case 3:
3540 i |= UPS_HIGH_SPEED;
3541 break;
3542 case 2:
3543 i |= UPS_LOW_SPEED;
3544 break;
3545 case 1:
3546 /* FULL speed */
3547 break;
3548 default:
3549 i |= UPS_OTHER_SPEED;
3550 break;
3551 }
3552
3553 if (v & XHCI_PS_CCS)
3554 i |= UPS_CURRENT_CONNECT_STATUS;
3555 if (v & XHCI_PS_PED)
3556 i |= UPS_PORT_ENABLED;
3557 if (v & XHCI_PS_OCA)
3558 i |= UPS_OVERCURRENT_INDICATOR;
3559 if (v & XHCI_PS_PR)
3560 i |= UPS_RESET;
3561 if (v & XHCI_PS_PP) {
3562 /*
3563 * The USB 3.0 RH is using the
3564 * USB 2.0's power bit
3565 */
3566 i |= UPS_PORT_POWER;
3567 }
3568 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3569
3570 i = 0;
3571 if (v & XHCI_PS_CSC)
3572 i |= UPS_C_CONNECT_STATUS;
3573 if (v & XHCI_PS_PEC)
3574 i |= UPS_C_PORT_ENABLED;
3575 if (v & XHCI_PS_OCC)
3576 i |= UPS_C_OVERCURRENT_INDICATOR;
3577 if (v & XHCI_PS_WRC)
3578 i |= UPS_C_BH_PORT_RESET;
3579 if (v & XHCI_PS_PRC)
3580 i |= UPS_C_PORT_RESET;
3581 if (v & XHCI_PS_PLC)
3582 i |= UPS_C_PORT_LINK_STATE;
3583 if (v & XHCI_PS_CEC)
3584 i |= UPS_C_PORT_CONFIG_ERROR;
3585
3586 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3587 len = sizeof(sc->sc_hub_desc.ps);
3588 break;
3589
3590 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3591 err = USB_ERR_IOERROR;
3592 goto done;
3593
3594 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3595 break;
3596
3597 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3598
3599 i = index >> 8;
3600 index &= 0x00FF;
3601
3602 if ((index < 1) ||
3603 (index > sc->sc_noport)) {
3604 err = USB_ERR_IOERROR;
3605 goto done;
3606 }
3607
3608 port = XHCI_PORTSC(index);
3609 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3610
3611 switch (value) {
3612 case UHF_PORT_U1_TIMEOUT:
3613 if (XHCI_PS_SPEED_GET(v) != 4) {
3614 err = USB_ERR_IOERROR;
3615 goto done;
3616 }
3617 port = XHCI_PORTPMSC(index);
3618 v = XREAD4(sc, oper, port);
3619 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3620 v |= XHCI_PM3_U1TO_SET(i);
3621 XWRITE4(sc, oper, port, v);
3622 break;
3623 case UHF_PORT_U2_TIMEOUT:
3624 if (XHCI_PS_SPEED_GET(v) != 4) {
3625 err = USB_ERR_IOERROR;
3626 goto done;
3627 }
3628 port = XHCI_PORTPMSC(index);
3629 v = XREAD4(sc, oper, port);
3630 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3631 v |= XHCI_PM3_U2TO_SET(i);
3632 XWRITE4(sc, oper, port, v);
3633 break;
3634 case UHF_BH_PORT_RESET:
3635 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3636 break;
3637 case UHF_PORT_LINK_STATE:
3638 XWRITE4(sc, oper, port, v |
3639 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3640 /* 4ms settle time */
3641 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250);
3642 break;
3643 case UHF_PORT_ENABLE:
3644 DPRINTFN(3, "set port enable %d\n", index);
3645 break;
3646 case UHF_PORT_SUSPEND:
3647 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3648 j = XHCI_PS_SPEED_GET(v);
3649 if ((j < 1) || (j > 3)) {
3650 /* non-supported speed */
3651 err = USB_ERR_IOERROR;
3652 goto done;
3653 }
3654 XWRITE4(sc, oper, port, v |
3655 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3656 break;
3657 case UHF_PORT_RESET:
3658 DPRINTFN(6, "reset port %d\n", index);
3659 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3660 break;
3661 case UHF_PORT_POWER:
3662 DPRINTFN(3, "set port power %d\n", index);
3663 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3664 break;
3665 case UHF_PORT_TEST:
3666 DPRINTFN(3, "set port test %d\n", index);
3667 break;
3668 case UHF_PORT_INDICATOR:
3669 DPRINTFN(3, "set port indicator %d\n", index);
3670
3671 v &= ~XHCI_PS_PIC_SET(3);
3672 v |= XHCI_PS_PIC_SET(1);
3673
3674 XWRITE4(sc, oper, port, v);
3675 break;
3676 default:
3677 err = USB_ERR_IOERROR;
3678 goto done;
3679 }
3680 break;
3681
3682 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3683 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3684 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3685 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3686 break;
3687 default:
3688 err = USB_ERR_IOERROR;
3689 goto done;
3690 }
3691 done:
3692 *plength = len;
3693 *pptr = ptr;
3694 return (err);
3695 }
3696
3697 static void
xhci_xfer_setup(struct usb_setup_params * parm)3698 xhci_xfer_setup(struct usb_setup_params *parm)
3699 {
3700 struct usb_page_search page_info;
3701 struct usb_page_cache *pc;
3702 struct xhci_softc *sc;
3703 struct usb_xfer *xfer;
3704 void *last_obj;
3705 uint32_t ntd;
3706 uint32_t n;
3707
3708 sc = XHCI_BUS2SC(parm->udev->bus);
3709 xfer = parm->curr_xfer;
3710
3711 /*
3712 * The proof for the "ntd" formula is illustrated like this:
3713 *
3714 * +------------------------------------+
3715 * | |
3716 * | |remainder -> |
3717 * | +-----+---+ |
3718 * | | xxx | x | frm 0 |
3719 * | +-----+---++ |
3720 * | | xxx | xx | frm 1 |
3721 * | +-----+----+ |
3722 * | ... |
3723 * +------------------------------------+
3724 *
3725 * "xxx" means a completely full USB transfer descriptor
3726 *
3727 * "x" and "xx" means a short USB packet
3728 *
3729 * For the remainder of an USB transfer modulo
3730 * "max_data_length" we need two USB transfer descriptors.
3731 * One to transfer the remaining data and one to finalise with
3732 * a zero length packet in case the "force_short_xfer" flag is
3733 * set. We only need two USB transfer descriptors in the case
3734 * where the transfer length of the first one is a factor of
3735 * "max_frame_size". The rest of the needed USB transfer
3736 * descriptors is given by the buffer size divided by the
3737 * maximum data payload.
3738 */
3739 parm->hc_max_packet_size = 0x400;
3740 parm->hc_max_packet_count = 16 * 3;
3741 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3742
3743 xfer->flags_int.bdma_enable = 1;
3744
3745 usbd_transfer_setup_sub(parm);
3746
3747 if (xfer->flags_int.isochronous_xfr) {
3748 ntd = ((1 * xfer->nframes)
3749 + (xfer->max_data_length / xfer->max_hc_frame_size));
3750 } else if (xfer->flags_int.control_xfr) {
3751 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3752 + (xfer->max_data_length / xfer->max_hc_frame_size));
3753 } else {
3754 ntd = ((2 * xfer->nframes)
3755 + (xfer->max_data_length / xfer->max_hc_frame_size));
3756 }
3757
3758 alloc_dma_set:
3759
3760 if (parm->err)
3761 return;
3762
3763 /*
3764 * Allocate queue heads and transfer descriptors
3765 */
3766 last_obj = NULL;
3767
3768 if (usbd_transfer_setup_sub_malloc(
3769 parm, &pc, sizeof(struct xhci_td),
3770 XHCI_TD_ALIGN, ntd)) {
3771 parm->err = USB_ERR_NOMEM;
3772 return;
3773 }
3774 if (parm->buf) {
3775 for (n = 0; n != ntd; n++) {
3776 struct xhci_td *td;
3777
3778 usbd_get_page(pc + n, 0, &page_info);
3779
3780 td = page_info.buffer;
3781
3782 /* init TD */
3783 td->td_self = page_info.physaddr;
3784 td->obj_next = last_obj;
3785 td->page_cache = pc + n;
3786
3787 last_obj = td;
3788
3789 usb_pc_cpu_flush(pc + n);
3790 }
3791 }
3792 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3793
3794 if (!xfer->flags_int.curr_dma_set) {
3795 xfer->flags_int.curr_dma_set = 1;
3796 goto alloc_dma_set;
3797 }
3798 }
3799
3800 static usb_error_t
xhci_configure_reset_endpoint(struct usb_xfer * xfer)3801 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3802 {
3803 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3804 struct usb_page_search buf_inp;
3805 struct usb_device *udev;
3806 struct xhci_endpoint_ext *pepext;
3807 struct usb_endpoint_descriptor *edesc;
3808 struct usb_page_cache *pcinp;
3809 usb_error_t err;
3810 usb_stream_t stream_id;
3811 uint8_t index;
3812 uint8_t epno;
3813
3814 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3815 xfer->endpoint->edesc);
3816
3817 udev = xfer->xroot->udev;
3818 index = udev->controller_slot_id;
3819
3820 pcinp = &sc->sc_hw.devs[index].input_pc;
3821
3822 usbd_get_page(pcinp, 0, &buf_inp);
3823
3824 edesc = xfer->endpoint->edesc;
3825
3826 epno = edesc->bEndpointAddress;
3827 stream_id = xfer->stream_id;
3828
3829 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3830 epno |= UE_DIR_IN;
3831
3832 epno = XHCI_EPNO2EPID(epno);
3833
3834 if (epno == 0)
3835 return (USB_ERR_NO_PIPE); /* invalid */
3836
3837 XHCI_CMD_LOCK(sc);
3838
3839 /* configure endpoint */
3840
3841 err = xhci_configure_endpoint_by_xfer(xfer);
3842
3843 if (err != 0) {
3844 XHCI_CMD_UNLOCK(sc);
3845 return (err);
3846 }
3847
3848 /*
3849 * Get the endpoint into the stopped state according to the
3850 * endpoint context state diagram in the XHCI specification:
3851 */
3852
3853 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3854
3855 if (err != 0)
3856 DPRINTF("Could not stop endpoint %u\n", epno);
3857
3858 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3859
3860 if (err != 0)
3861 DPRINTF("Could not reset endpoint %u\n", epno);
3862
3863 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3864 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3865 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3866 stream_id, epno, index);
3867
3868 if (err != 0)
3869 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3870
3871 /*
3872 * Get the endpoint into the running state according to the
3873 * endpoint context state diagram in the XHCI specification:
3874 */
3875
3876 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3877
3878 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3879
3880 if (err != 0)
3881 DPRINTF("Could not configure endpoint %u\n", epno);
3882
3883 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3884
3885 if (err != 0)
3886 DPRINTF("Could not configure endpoint %u\n", epno);
3887
3888 XHCI_CMD_UNLOCK(sc);
3889
3890 return (0);
3891 }
3892
3893 static void
xhci_xfer_unsetup(struct usb_xfer * xfer)3894 xhci_xfer_unsetup(struct usb_xfer *xfer)
3895 {
3896 return;
3897 }
3898
3899 static void
xhci_start_dma_delay(struct usb_xfer * xfer)3900 xhci_start_dma_delay(struct usb_xfer *xfer)
3901 {
3902 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3903
3904 /* put transfer on interrupt queue (again) */
3905 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3906
3907 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3908 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3909 }
3910
3911 static void
xhci_configure_msg(struct usb_proc_msg * pm)3912 xhci_configure_msg(struct usb_proc_msg *pm)
3913 {
3914 struct xhci_softc *sc;
3915 struct xhci_endpoint_ext *pepext;
3916 struct usb_xfer *xfer;
3917
3918 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3919
3920 restart:
3921 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3922
3923 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3924 xfer->endpoint->edesc);
3925
3926 if ((pepext->trb_halted != 0) ||
3927 (pepext->trb_running == 0)) {
3928
3929 uint16_t i;
3930
3931 /* clear halted and running */
3932 pepext->trb_halted = 0;
3933 pepext->trb_running = 0;
3934
3935 /* nuke remaining buffered transfers */
3936
3937 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3938 XHCI_MAX_STREAMS); i++) {
3939 /*
3940 * NOTE: We need to use the timeout
3941 * error code here else existing
3942 * isochronous clients can get
3943 * confused:
3944 */
3945 if (pepext->xfer[i] != NULL) {
3946 xhci_device_done(pepext->xfer[i],
3947 USB_ERR_TIMEOUT);
3948 }
3949 }
3950
3951 /*
3952 * NOTE: The USB transfer cannot vanish in
3953 * this state!
3954 */
3955
3956 USB_BUS_UNLOCK(&sc->sc_bus);
3957
3958 xhci_configure_reset_endpoint(xfer);
3959
3960 USB_BUS_LOCK(&sc->sc_bus);
3961
3962 /* check if halted is still cleared */
3963 if (pepext->trb_halted == 0) {
3964 pepext->trb_running = 1;
3965 memset(pepext->trb_index, 0,
3966 sizeof(pepext->trb_index));
3967 }
3968 goto restart;
3969 }
3970
3971 if (xfer->flags_int.did_dma_delay) {
3972
3973 /* remove transfer from interrupt queue (again) */
3974 usbd_transfer_dequeue(xfer);
3975
3976 /* we are finally done */
3977 usb_dma_delay_done_cb(xfer);
3978
3979 /* queue changed - restart */
3980 goto restart;
3981 }
3982 }
3983
3984 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3985
3986 /* try to insert xfer on HW queue */
3987 xhci_transfer_insert(xfer);
3988
3989 /* try to multi buffer */
3990 xhci_device_generic_multi_enter(xfer->endpoint,
3991 xfer->stream_id, NULL);
3992 }
3993 }
3994
3995 static void
xhci_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)3996 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3997 struct usb_endpoint *ep)
3998 {
3999 struct xhci_endpoint_ext *pepext;
4000
4001 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4002 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4003
4004 if (udev->parent_hub == NULL) {
4005 /* root HUB has special endpoint handling */
4006 return;
4007 }
4008
4009 ep->methods = &xhci_device_generic_methods;
4010
4011 pepext = xhci_get_endpoint_ext(udev, edesc);
4012
4013 USB_BUS_LOCK(udev->bus);
4014 pepext->trb_halted = 1;
4015 pepext->trb_running = 0;
4016 USB_BUS_UNLOCK(udev->bus);
4017 }
4018
4019 static void
xhci_ep_uninit(struct usb_device * udev,struct usb_endpoint * ep)4020 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4021 {
4022
4023 }
4024
4025 static void
xhci_ep_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)4026 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4027 {
4028 struct xhci_endpoint_ext *pepext;
4029
4030 DPRINTF("\n");
4031
4032 if (udev->flags.usb_mode != USB_MODE_HOST) {
4033 /* not supported */
4034 return;
4035 }
4036 if (udev->parent_hub == NULL) {
4037 /* root HUB has special endpoint handling */
4038 return;
4039 }
4040
4041 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4042
4043 USB_BUS_LOCK(udev->bus);
4044 pepext->trb_halted = 1;
4045 pepext->trb_running = 0;
4046 USB_BUS_UNLOCK(udev->bus);
4047 }
4048
4049 static usb_error_t
xhci_device_init(struct usb_device * udev)4050 xhci_device_init(struct usb_device *udev)
4051 {
4052 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4053 usb_error_t err;
4054 uint8_t temp;
4055
4056 /* no init for root HUB */
4057 if (udev->parent_hub == NULL)
4058 return (0);
4059
4060 XHCI_CMD_LOCK(sc);
4061
4062 /* set invalid default */
4063
4064 udev->controller_slot_id = sc->sc_noslot + 1;
4065
4066 /* try to get a new slot ID from the XHCI */
4067
4068 err = xhci_cmd_enable_slot(sc, &temp);
4069
4070 if (err) {
4071 XHCI_CMD_UNLOCK(sc);
4072 return (err);
4073 }
4074
4075 if (temp > sc->sc_noslot) {
4076 XHCI_CMD_UNLOCK(sc);
4077 return (USB_ERR_BAD_ADDRESS);
4078 }
4079
4080 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4081 DPRINTF("slot %u already allocated.\n", temp);
4082 XHCI_CMD_UNLOCK(sc);
4083 return (USB_ERR_BAD_ADDRESS);
4084 }
4085
4086 /* store slot ID for later reference */
4087
4088 udev->controller_slot_id = temp;
4089
4090 /* reset data structure */
4091
4092 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4093
4094 /* set mark slot allocated */
4095
4096 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4097
4098 err = xhci_alloc_device_ext(udev);
4099
4100 XHCI_CMD_UNLOCK(sc);
4101
4102 /* get device into default state */
4103
4104 if (err == 0)
4105 err = xhci_set_address(udev, NULL, 0);
4106
4107 return (err);
4108 }
4109
4110 static void
xhci_device_uninit(struct usb_device * udev)4111 xhci_device_uninit(struct usb_device *udev)
4112 {
4113 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4114 uint8_t index;
4115
4116 /* no init for root HUB */
4117 if (udev->parent_hub == NULL)
4118 return;
4119
4120 XHCI_CMD_LOCK(sc);
4121
4122 index = udev->controller_slot_id;
4123
4124 if (index <= sc->sc_noslot) {
4125 xhci_cmd_disable_slot(sc, index);
4126 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4127
4128 /* free device extension */
4129 xhci_free_device_ext(udev);
4130 }
4131
4132 XHCI_CMD_UNLOCK(sc);
4133 }
4134
4135 static void
xhci_get_dma_delay(struct usb_device * udev,uint32_t * pus)4136 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4137 {
4138 /*
4139 * Wait until the hardware has finished any possible use of
4140 * the transfer descriptor(s)
4141 */
4142 *pus = 2048; /* microseconds */
4143 }
4144
4145 static void
xhci_device_resume(struct usb_device * udev)4146 xhci_device_resume(struct usb_device *udev)
4147 {
4148 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4149 uint8_t index;
4150 uint8_t n;
4151 uint8_t p;
4152
4153 DPRINTF("\n");
4154
4155 /* check for root HUB */
4156 if (udev->parent_hub == NULL)
4157 return;
4158
4159 index = udev->controller_slot_id;
4160
4161 XHCI_CMD_LOCK(sc);
4162
4163 /* blindly resume all endpoints */
4164
4165 USB_BUS_LOCK(udev->bus);
4166
4167 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4168 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4169 XWRITE4(sc, door, XHCI_DOORBELL(index),
4170 n | XHCI_DB_SID_SET(p));
4171 }
4172 }
4173
4174 USB_BUS_UNLOCK(udev->bus);
4175
4176 XHCI_CMD_UNLOCK(sc);
4177 }
4178
4179 static void
xhci_device_suspend(struct usb_device * udev)4180 xhci_device_suspend(struct usb_device *udev)
4181 {
4182 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4183 uint8_t index;
4184 uint8_t n;
4185 usb_error_t err;
4186
4187 DPRINTF("\n");
4188
4189 /* check for root HUB */
4190 if (udev->parent_hub == NULL)
4191 return;
4192
4193 index = udev->controller_slot_id;
4194
4195 XHCI_CMD_LOCK(sc);
4196
4197 /* blindly suspend all endpoints */
4198
4199 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4200 err = xhci_cmd_stop_ep(sc, 1, n, index);
4201 if (err != 0) {
4202 DPRINTF("Failed to suspend endpoint "
4203 "%u on slot %u (ignored).\n", n, index);
4204 }
4205 }
4206
4207 XHCI_CMD_UNLOCK(sc);
4208 }
4209
4210 static void
xhci_set_hw_power(struct usb_bus * bus)4211 xhci_set_hw_power(struct usb_bus *bus)
4212 {
4213 DPRINTF("\n");
4214 }
4215
4216 static void
xhci_device_state_change(struct usb_device * udev)4217 xhci_device_state_change(struct usb_device *udev)
4218 {
4219 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4220 struct usb_page_search buf_inp;
4221 usb_error_t err;
4222 uint8_t index;
4223
4224 /* check for root HUB */
4225 if (udev->parent_hub == NULL)
4226 return;
4227
4228 index = udev->controller_slot_id;
4229
4230 DPRINTF("\n");
4231
4232 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4233 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4234 &sc->sc_hw.devs[index].tt);
4235 if (err != 0)
4236 sc->sc_hw.devs[index].nports = 0;
4237 }
4238
4239 XHCI_CMD_LOCK(sc);
4240
4241 switch (usb_get_device_state(udev)) {
4242 case USB_STATE_POWERED:
4243 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4244 break;
4245
4246 /* set default state */
4247 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4248
4249 /* reset number of contexts */
4250 sc->sc_hw.devs[index].context_num = 0;
4251
4252 err = xhci_cmd_reset_dev(sc, index);
4253
4254 if (err != 0) {
4255 DPRINTF("Device reset failed "
4256 "for slot %u.\n", index);
4257 }
4258 break;
4259
4260 case USB_STATE_ADDRESSED:
4261 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4262 break;
4263
4264 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4265
4266 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4267
4268 if (err) {
4269 DPRINTF("Failed to deconfigure "
4270 "slot %u.\n", index);
4271 }
4272 break;
4273
4274 case USB_STATE_CONFIGURED:
4275 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4276 break;
4277
4278 /* set configured state */
4279 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4280
4281 /* reset number of contexts */
4282 sc->sc_hw.devs[index].context_num = 0;
4283
4284 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4285
4286 xhci_configure_mask(udev, 3, 0);
4287
4288 err = xhci_configure_device(udev);
4289 if (err != 0) {
4290 DPRINTF("Could not configure device "
4291 "at slot %u.\n", index);
4292 }
4293
4294 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4295 if (err != 0) {
4296 DPRINTF("Could not evaluate device "
4297 "context at slot %u.\n", index);
4298 }
4299 break;
4300
4301 default:
4302 break;
4303 }
4304 XHCI_CMD_UNLOCK(sc);
4305 }
4306
4307 static usb_error_t
xhci_set_endpoint_mode(struct usb_device * udev,struct usb_endpoint * ep,uint8_t ep_mode)4308 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4309 uint8_t ep_mode)
4310 {
4311 switch (ep_mode) {
4312 case USB_EP_MODE_DEFAULT:
4313 return (0);
4314 case USB_EP_MODE_STREAMS:
4315 if (xhcistreams == 0 ||
4316 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4317 udev->speed != USB_SPEED_SUPER)
4318 return (USB_ERR_INVAL);
4319 return (0);
4320 default:
4321 return (USB_ERR_INVAL);
4322 }
4323 }
4324
4325 static const struct usb_bus_methods xhci_bus_methods = {
4326 .endpoint_init = xhci_ep_init,
4327 .endpoint_uninit = xhci_ep_uninit,
4328 .xfer_setup = xhci_xfer_setup,
4329 .xfer_unsetup = xhci_xfer_unsetup,
4330 .get_dma_delay = xhci_get_dma_delay,
4331 .device_init = xhci_device_init,
4332 .device_uninit = xhci_device_uninit,
4333 .device_resume = xhci_device_resume,
4334 .device_suspend = xhci_device_suspend,
4335 .set_hw_power = xhci_set_hw_power,
4336 .roothub_exec = xhci_roothub_exec,
4337 .xfer_poll = xhci_do_poll,
4338 .start_dma_delay = xhci_start_dma_delay,
4339 .set_address = xhci_set_address,
4340 .clear_stall = xhci_ep_clear_stall,
4341 .device_state_change = xhci_device_state_change,
4342 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4343 .set_endpoint_mode = xhci_set_endpoint_mode,
4344 };
4345