1 /* Copyright 2014-2016 James Laird-Wah
2 Copyright 2004-2006, 2013 Theo Berkau
3
4 This file is part of Yabause.
5
6 Yabause is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 Yabause is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with Yabause; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 /*! \file ygr.c
22 \brief YGR implementation (CD block LSI)
23 */
24
25 #include "core.h"
26 #include "sh7034.h"
27 #include "assert.h"
28 #include "memory.h"
29 #include "debug.h"
30 #include <stdarg.h>
31 #ifdef ENABLE_TSUNAMI
32 #include "tsunami/yab_tsunami.h"
33 #endif
34 #include "mpeg_card.h"
35 #ifdef WIN32
36 #include "windows.h"
37 #endif
38
39 void Cs2Exec(u32 timing);
40
41 //#define YGR_SH1_RW_DEBUG
42 #ifdef YGR_SH1_RW_DEBUG
43 #define YGR_SH1_RW_LOG(...) DebugPrintf(MainLog, __FILE__, __LINE__, __VA_ARGS__)
44 #else
45 #define YGR_SH1_RW_LOG(...)
46 #endif
47
48 // ygr connections
49 // ygr <=> cd signal processor (on cd drive board)
50 // ygr <=> sh1 (aka sh7034)
51 // ygr <=> a-bus (sh2 interface)
52 // ygr <=> vdp2 (mpeg video)
53 // ygr <=> scsp (cd audio)
54
55
56 #define FIFO_SIZE 4096
57 #define FIFO_MASK (FIFO_SIZE-1)
58
59 struct Ygr
60 {
61 struct Regs
62 {
63 u32 DTR;
64 u16 UNKNOWN;
65 u16 HIRQ;
66 u16 HIRQMASK; // Masks bits from HIRQ -only- when generating A-bus interrupts
67
68 //command regs
69 //a-bus reads RR, writes to CR
70 u16 CR1;
71 u16 CR2;
72 u16 CR3;
73 u16 CR4;
74
75 //response regs
76 //sh1-bus writes to RR, reads CR
77 u16 RR1;
78 u16 RR2;
79 u16 RR3;
80 u16 RR4;
81
82 u16 MPEGRGB;
83 }regs;
84
85 int fifo_ptr;
86 u16 fifo[FIFO_SIZE];
87 u16 transfer_ctrl;
88
89 int fifo_read_ptr;
90 int fifo_write_ptr;
91 int fifo_num_stored;
92
93 u16 cdirq_flags;
94
95 int mbx_status;
96 u16 fake_fifo;
97 u16 reg_0c;
98 u16 reg_1a;
99 u16 reg_1c;
100 }ygr_cxt = { 0 };
101
102
103
read_fifo()104 u16 read_fifo()
105 {
106 int ptr = ygr_cxt.fifo_read_ptr;
107
108 if(ygr_cxt.transfer_ctrl & 4)
109 {
110 assert(ygr_cxt.fifo_num_stored > 0);
111
112 if (ygr_cxt.fifo_num_stored <= 0)
113 {
114 #ifdef WIN32
115 DebugBreak();
116 #endif
117 }
118 }
119
120 ygr_cxt.fifo_read_ptr++;
121 ygr_cxt.fifo_read_ptr &= FIFO_MASK;
122
123 ygr_cxt.fifo_num_stored--;
124
125 if (ygr_cxt.fifo_num_stored < 0)
126 ygr_cxt.fifo_num_stored = 0;
127
128 return ygr_cxt.fifo[ptr];
129 }
130
write_fifo(u16 data)131 void write_fifo(u16 data)
132 {
133
134 if (ygr_cxt.fifo_num_stored == FIFO_SIZE)
135 assert(0);
136
137 ygr_cxt.fifo[ygr_cxt.fifo_write_ptr++] = data;
138 ygr_cxt.fifo_write_ptr &= FIFO_MASK;
139 ygr_cxt.fifo_num_stored++;
140 }
141
fifo_full()142 int fifo_full()
143 {
144 #ifdef ENABLE_TSUNAMI
145 if (ygr_cxt.fifo_num_stored == FIFO_SIZE)
146 tsunami_log_value("FIFO_FULL", 1, 1);
147 else
148 tsunami_log_value("FIFO_FULL", 0, 1);
149 #endif
150
151 return ygr_cxt.fifo_num_stored == FIFO_SIZE;
152 }
153
154
fifo_empty()155 int fifo_empty()
156 {
157 return ygr_cxt.fifo_num_stored == 0;
158 }
159
160 //#define WRITE_FIFO_LOG
161 //#define VERIFY_FIFO_LOG
162
make_fifo_log(u32 data)163 void make_fifo_log(u32 data)
164 {
165 #if defined WRITE_FIFO_LOG && !defined(VERIFY_FIFO_LOG)
166 static FILE * fp;
167 static int started = 0;
168 static int count = 0;
169
170 if (!started)
171 {
172 fp = fopen("C:/yabause/fifo_log.txt", "w");
173 started = 1;
174 }
175
176 fprintf(fp, "%08X, %d\n", data, count);
177 count++;
178 #endif
179 }
180 static int ygr_count = 0;
verify_fifo_log(u32 data_in)181 void verify_fifo_log(u32 data_in)
182 {
183 #if defined VERIFY_FIFO_LOG && !defined(WRITE_FIFO_LOG)
184 static FILE * fp;
185 static int started = 0;
186 u32 correct_data = 0;
187 int correct_count = 0;
188 int retval = 0;
189 if (!started)
190 {
191 fp = fopen("C:/yabause/fifo_log.txt", "r");
192 started = 1;
193 }
194
195 retval = fscanf(fp, "%08X, %d\n", &correct_data, &correct_count);
196
197 if (retval == 2)
198 {
199 assert(data_in == correct_data);
200 assert(ygr_count == correct_count);
201 }
202 ygr_count++;
203 #endif
204
205 }
206
ygr_dreq_asserted()207 int ygr_dreq_asserted()
208 {
209 if (fifo_empty() && ((ygr_cxt.transfer_ctrl & 5) == 5))//put / get sector
210 {
211 return 0;
212 }
213 else if (fifo_full())
214 {
215 #ifdef ENABLE_TSUNAMI
216 tsunami_log_value("DREQ", 0, 1);
217 #endif
218 return 0;
219 }
220 else
221 {
222 int dreq = (ygr_cxt.transfer_ctrl >> 2) & 1;
223 #ifdef ENABLE_TSUNAMI
224 tsunami_log_value("DREQ", dreq, 1);
225 #endif
226 return dreq;
227 }
228 }
229
230
sh2_a_bus_check_wait(u32 addr,int size)231 int sh2_a_bus_check_wait(u32 addr, int size)
232 {
233 if (((addr & 0x7FFF) <= 0xFFF) && ((addr &= 0x3F) <= 2))
234 {
235 //if something is in the fifo, no wait
236 if (size == 1 && ygr_cxt.fifo_num_stored)//word size
237 return 0;
238 else if (size == 2 && ygr_cxt.fifo_num_stored >= 2)//long size
239 return 0;
240 else
241 {
242 if ((ygr_cxt.transfer_ctrl >> 2) & 1)
243 return 1;//more data expected
244 else
245 return 0;
246 }
247 }
248
249 return 0;
250 }
251
252
ygr_sh1_read_byte(u32 addr)253 u8 ygr_sh1_read_byte(u32 addr)
254 {
255 assert(0);
256 CDTRACE("rblsi: %08X\n", addr);
257 YGR_SH1_RW_LOG("ygr_sh1_read_byte 0x%08x", addr );
258 return 0;
259 }
260
ygr_sh1_read_word(u32 addr)261 u16 ygr_sh1_read_word(u32 addr)
262 {
263 if ((addr & 0xf00000) == 0x100000)
264 {
265 return mpeg_card_read_word(addr);
266 }
267 CDTRACE("rwlsi: %08X\n", addr);
268 switch (addr & 0xffff) {
269 case 0:
270 {
271 u16 val = read_fifo();
272 #ifdef ENABLE_TSUNAMI
273 tsunami_log_value("SH1_R_FIFO", val, 16);
274 #endif
275 return val;
276 }
277 case 2:
278 return ygr_cxt.transfer_ctrl;
279 case 4:
280 return ygr_cxt.mbx_status;
281 case 0x6:
282 return ygr_cxt.cdirq_flags;
283 case 8:
284 return ygr_cxt.regs.UNKNOWN;
285 case 0xa:
286 return ygr_cxt.regs.HIRQMASK;
287 case 0x10: // CR1
288 return ygr_cxt.regs.CR1;
289 case 0x12: // CR2
290 return ygr_cxt.regs.CR2;
291 case 0x14: // CR3
292 return ygr_cxt.regs.CR3;
293 case 0x16: // CR4
294 return ygr_cxt.regs.CR4;
295 case 0x1a:
296 return ygr_cxt.reg_1a;
297 case 0x1c:
298 return ygr_cxt.reg_1c;
299 }
300 YGR_SH1_RW_LOG("ygr_sh1_read_word 0x%08x", addr);
301 assert(0);
302 return 0;
303 }
304
ygr_sh1_read_long(u32 addr)305 u32 ygr_sh1_read_long(u32 addr)
306 {
307 CDTRACE("rllsi: %08X\n", addr);
308 YGR_SH1_RW_LOG("ygr_sh1_read_long 0x%08x", addr);
309 return 0;
310 }
311
ygr_sh1_write_byte(u32 addr,u8 data)312 void ygr_sh1_write_byte(u32 addr,u8 data)
313 {
314 assert(0);
315 CDTRACE("wblsi: %08X %02X\n", addr, data);
316 YGR_SH1_RW_LOG("ygr_sh1_write_byte 0x%08x 0x%02x", addr, data);
317 }
318
ygr_sh1_write_word(u32 addr,u16 data)319 void ygr_sh1_write_word(u32 addr, u16 data)
320 {
321 if ((addr & 0xf00000) == 0x100000)
322 {
323 mpeg_card_write_word(addr, data);
324 return;
325 }
326 CDTRACE("wwlsi: %08X %04X\n", addr, data);
327 switch (addr & 0xffff) {
328 case 0:
329 #ifdef ENABLE_TSUNAMI
330 tsunami_log_value("SH1_W_FIFO", data, 16);
331 #endif
332 write_fifo(data);
333 return;
334 case 2:
335 if (data & 2)
336 {
337 ygr_cxt.fifo_read_ptr = 0;
338 ygr_cxt.fifo_write_ptr = 0;
339 ygr_cxt.fifo_num_stored = 0;
340 }
341 ygr_cxt.transfer_ctrl = data;
342 return;
343 case 4:
344 ygr_cxt.mbx_status = data;
345 return;
346 case 0x6:
347 ygr_cxt.cdirq_flags = data;
348 return;
349 case 8:
350 ygr_cxt.regs.UNKNOWN = data & 3;
351 return;
352 case 0xa:
353 ygr_cxt.regs.HIRQMASK = data & 0x70;
354 return;
355 case 0xc:
356 ygr_cxt.reg_0c = data;
357 return;
358 case 0x10: // CR1
359 ygr_cxt.regs.RR1 = data;
360 return;
361 case 0x12: // CR2
362 ygr_cxt.regs.RR2 = data;
363 return;
364 case 0x14: // CR3
365 ygr_cxt.regs.RR3 = data;
366 return;
367 case 0x16: // CR4
368 ygr_cxt.regs.RR4 = data;
369 return;
370 case 0x1e:
371 ygr_cxt.regs.HIRQ |= data;
372 return;
373 case 0x1a:
374 ygr_cxt.reg_1a = data;
375 return;
376 }
377 assert(0);
378 YGR_SH1_RW_LOG("ygr_sh1_write_word 0x%08x 0x%04x", addr, data);
379 }
380
ygr_sh1_write_long(u32 addr,u32 data)381 void ygr_sh1_write_long(u32 addr, u32 data)
382 {
383 CDTRACE("wblsi: %08X %08X\n", addr, data);
384 YGR_SH1_RW_LOG("ygr_sh1_write_long 0x%08x 0x%08x", addr, data);
385 }
386
387 //////////////////////////////////////////////////////////////////////////////
388
lle_trace_log(const char * format,...)389 void lle_trace_log(const char * format, ...)
390 {
391 static int started = 0;
392 static FILE* fp = NULL;
393 va_list l;
394
395 if (!started)
396 {
397 fp = fopen("C:/yabause/lle_log.txt", "w");
398
399 if (!fp)
400 {
401 return;
402 }
403 started = 1;
404 }
405
406 va_start(l, format);
407 vfprintf(fp, format, l);
408 va_end(l);
409 }
410
411 //#define WANT_LLE_TRACE
412
413 #ifdef WANT_LLE_TRACE
414 #define LLECDLOG(...) lle_trace_log(__VA_ARGS__)
415 #else
416 #define LLECDLOG(...)
417 #endif
418
419 void ygr_a_bus_cd_cmd_log(void);
420
421
get_status(u16 cr1)422 char* get_status(u16 cr1)
423 {
424 switch ((cr1 >> 8) & 0xf)
425 {
426 case 0:
427 return "busy";
428 case 1:
429 return "paused";
430 case 2:
431 return "standby";
432 case 3:
433 return "playing";
434 case 4:
435 return "seeking";
436 case 5:
437 return "scanning";
438 case 7:
439 return "tray open";
440 case 8:
441 return "retrying";
442 case 9:
443 return "read data error";
444 case 0xa:
445 return "fatal error";
446 default:
447 return "unknown";
448 }
449
450 return "get status error";
451 }
452
453 //replacements for Cs2ReadWord etc
ygr_a_bus_read_word(u32 addr)454 u16 FASTCALL ygr_a_bus_read_word(u32 addr) {
455 u16 val = 0;
456
457 if ((addr & 0x7FFF) <= 0xFFF)
458 {
459 addr &= 0x3F;
460
461 switch (addr) {
462 case 0x00:
463 case 0x02:
464 // transfer info
465 {
466 u16 val = read_fifo();
467 verify_fifo_log(val);
468 #ifdef ENABLE_TSUNAMI
469 tsunami_log_value("SH2_R_FIFO", val, 16);
470 #endif
471 return val;
472 }
473 break;
474 case 0x08:
475 case 0x0A:
476 LLECDLOG("Cs2ReadWord %08X %04X\n", addr, ygr_cxt.regs.HIRQ);
477 return ygr_cxt.regs.HIRQ;
478 case 0x0C:
479 case 0x0E:
480 LLECDLOG("Cs2ReadWord %08X %04X\n", addr, ygr_cxt.regs.HIRQMASK);
481 return ygr_cxt.regs.HIRQMASK;
482 case 0x18:
483 case 0x1A:
484 LLECDLOG("Cs2ReadWord %08X %04X\n", addr, ygr_cxt.regs.RR1);
485 return ygr_cxt.regs.RR1;
486 case 0x1C:
487 case 0x1E:
488 LLECDLOG("Cs2ReadWord %08X %04X\n", addr, ygr_cxt.regs.RR2);
489 return ygr_cxt.regs.RR2;
490 case 0x20:
491 case 0x22:
492 LLECDLOG("Cs2ReadWord %08X %04X\n", addr, ygr_cxt.regs.RR3);
493 return ygr_cxt.regs.RR3;
494 case 0x24:
495 case 0x26:
496 LLECDLOG("Cs2ReadWord %08X %04X\n", addr, ygr_cxt.regs.RR4);
497 ygr_cxt.mbx_status |= 2;
498 CDLOG("abus cdb response: CR1: %04x CR2: %04x CR3: %04x CR4: %04x HIRQ: %04x Status: %s\n", ygr_cxt.regs.RR1, ygr_cxt.regs.RR2, ygr_cxt.regs.RR3, ygr_cxt.regs.RR4, ygr_cxt.regs.HIRQ, get_status(ygr_cxt.regs.RR1));
499 return ygr_cxt.regs.RR4;
500 case 0x28:
501 case 0x2A:
502 return ygr_cxt.regs.MPEGRGB;
503 default:
504 LOG("ygr\t: Undocumented register read %08X\n", addr);
505 break;
506 }
507 }
508 assert(0);
509 return val;
510 }
511
512 //////////////////////////////////////////////////////////////////////////////
513 #ifdef CDDEBUG
ygr_a_bus_cd_cmd_log(void)514 void ygr_a_bus_cd_cmd_log(void)
515 {
516 u16 instruction=ygr_cxt.regs.CR1 >> 8;
517
518 switch (instruction)
519 {
520 case 0x00:
521 CDLOG("abus cdb command: Get Status %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
522 break;
523 case 0x01:
524 CDLOG("abus cdb command: Get Hardware Info %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
525 break;
526 case 0x02:
527 CDLOG("abus cdb command: Get TOC %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
528 break;
529 case 0x03:
530 CDLOG("abus cdb command: Get Session Info %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
531 break;
532 case 0x04:
533 CDLOG("abus cdb command: Initialize CD System %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
534 break;
535 case 0x05:
536 CDLOG("abus cdb command: Open Tray %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
537 break;
538 case 0x06:
539 CDLOG("abus cdb command: End Data Transfer %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
540 break;
541 case 0x10:
542 CDLOG("abus cdb command: Play Disc %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
543 break;
544 case 0x11:
545 CDLOG("abus cdb command: Seek Disc %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
546 break;
547 case 0x12:
548 CDLOG("abus cdb command: Scan Disc %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
549 break;
550 case 0x20:
551 CDLOG("abus cdb command: Get Subcode QRW %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
552 break;
553 case 0x30:
554 CDLOG("abus cdb command: Set CD Device Connection %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
555 break;
556 case 0x31:
557 CDLOG("abus cdb command: Get CD Device Connection %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
558 break;
559 case 0x32:
560 CDLOG("abus cdb command: Get Last Buffer Destination %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
561 break;
562 case 0x40:
563 CDLOG("abus cdb command: Set Filter Range %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
564 break;
565 case 0x41:
566 CDLOG("abus cdb command: Get Filter Range %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
567 break;
568 case 0x42:
569 CDLOG("abus cdb command: Set Filter Subheader Conditions %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
570 break;
571 case 0x43:
572 CDLOG("abus cdb command: Get Filter Subheader Conditions %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
573 break;
574 case 0x44:
575 CDLOG("abus cdb command: Set Filter Mode %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
576 break;
577 case 0x45:
578 CDLOG("abus cdb command: Get Filter Mode %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
579 break;
580 case 0x46:
581 CDLOG("abus cdb command: Set Filter Connection %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
582 break;
583 case 0x47:
584 CDLOG("abus cdb command: Get Filter Connection %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
585 break;
586 case 0x48:
587 CDLOG("abus cdb command: Reset Selector %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
588 break;
589 case 0x50:
590 CDLOG("abus cdb command: Get Buffer Size %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
591 break;
592 case 0x51:
593 CDLOG("abus cdb command: Get Sector Number %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
594 break;
595 case 0x52:
596 CDLOG("abus cdb command: Calculate Actual Size %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
597 break;
598 case 0x53:
599 CDLOG("abus cdb command: Get Actual Size %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
600 break;
601 case 0x54:
602 CDLOG("abus cdb command: Get Sector Info %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
603 break;
604 case 0x55:
605 CDLOG("abus cdb command: Execute FAD Search %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
606 break;
607 case 0x56:
608 CDLOG("abus cdb command: Get FAD Search Results %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
609 break;
610 case 0x60:
611 CDLOG("abus cdb command: Set Sector Length %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
612 break;
613 case 0x61:
614 CDLOG("abus cdb command: Get Sector Data %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
615 break;
616 case 0x62:
617 CDLOG("abus cdb command: Delete Sector Data %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
618 break;
619 case 0x63:
620 CDLOG("abus cdb command: Get Then Delete Sector Data %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
621 break;
622 case 0x64:
623 CDLOG("abus cdb command: Put Sector Data %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
624 break;
625 case 0x65:
626 CDLOG("abus cdb command: Copy Sector Data %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
627 break;
628 case 0x66:
629 CDLOG("abus cdb command: Move Sector Data %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
630 break;
631 case 0x67:
632 CDLOG("abus cdb command: Get Copy Error %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
633 break;
634 case 0x70:
635 CDLOG("abus cdb command: Change Directory %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
636 break;
637 case 0x71:
638 CDLOG("abus cdb command: Read Directory %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
639 break;
640 case 0x72:
641 CDLOG("abus cdb command: Get File System Scope %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
642 break;
643 case 0x73:
644 CDLOG("abus cdb command: Get File Info %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
645 break;
646 case 0x74:
647 CDLOG("abus cdb command: Read File %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
648 break;
649 case 0x75:
650 CDLOG("abus cdb command: Abort File %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
651 break;
652 case 0x90:
653 CDLOG("abus cdb command: MPEG Get Status %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
654 break;
655 case 0x91:
656 CDLOG("abus cdb command: MPEG Get Interrupt %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
657 break;
658 case 0x92:
659 CDLOG("abus cdb command: MPEG Set Interrupt Mask %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2);
660 break;
661 case 0x93:
662 CDLOG("abus cdb command: MPEG Init %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2);
663 break;
664 case 0x94:
665 CDLOG("abus cdb command: MPEG Set Mode %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3);
666 break;
667 case 0x95:
668 CDLOG("abus cdb command: MPEG Play %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR4);
669 break;
670 case 0x96:
671 CDLOG("abus cdb command: MPEG Set Decoding Method %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR4);
672 break;
673 case 0x97:
674 CDLOG("abus cdb command: MPEG Out Decoding Sync %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR4);
675 break;
676 case 0x98:
677 CDLOG("abus cdb command: MPEG Get Timecode %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR4);
678 break;
679 case 0x99:
680 CDLOG("abus cdb command: MPEG Get PTS %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR4);
681 break;
682 case 0x9A:
683 CDLOG("abus cdb command: MPEG Set Connection %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
684 break;
685 case 0x9B:
686 CDLOG("abus cdb command: MPEG Get Connection %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
687 break;
688 case 0x9C:
689 CDLOG("abus cdb command: MPEG Change Connection %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
690 break;
691 case 0x9D:
692 CDLOG("abus cdb command: MPEG Set Stream %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
693 break;
694 case 0x9E:
695 CDLOG("abus cdb command: MPEG Get Stream %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
696 break;
697 case 0x9F:
698 CDLOG("abus cdb command: MPEG Get Picture Size %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
699 break;
700 case 0xA0:
701 CDLOG("abus cdb command: MPEG Display %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
702 break;
703 case 0xA1:
704 CDLOG("abus cdb command: MPEG Set Window %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
705 break;
706 case 0xA2:
707 CDLOG("abus cdb command: MPEG Set Border Color %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
708 break;
709 case 0xA3:
710 CDLOG("abus cdb command: MPEG Set Fade %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
711 break;
712 case 0xA4:
713 CDLOG("abus cdb command: MPEG Set Video Effects %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
714 break;
715 case 0xA5:
716 CDLOG("abus cdb command: MPEG Get Image %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
717 break;
718 case 0xA6:
719 CDLOG("abus cdb command: MPEG Set Image %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
720 break;
721 case 0xA7:
722 CDLOG("abus cdb command: MPEG Read Image %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
723 break;
724 case 0xA8:
725 CDLOG("abus cdb command: MPEG Write Image %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
726 break;
727 case 0xA9:
728 CDLOG("abus cdb command: MPEG Read Sector %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
729 break;
730 case 0xAA:
731 CDLOG("abus cdb command: MPEG Write Sector %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
732 break;
733 case 0xAE:
734 CDLOG("abus cdb command: MPEG Get LSI %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
735 break;
736 case 0xAF:
737 CDLOG("abus cdb command: MPEG Set LSI %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
738 break;
739 case 0xE0:
740 CDLOG("abus cdb command: Authenticate Device %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
741 break;
742 case 0xE1:
743 CDLOG("abus cdb command: Is Device Authenticated %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
744 break;
745 case 0xE2:
746 CDLOG("abus cdb command: Get MPEG ROM %04x %04x %04x %04x %04x\n", ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
747 break;
748 default:
749 CDLOG("abus cdb command: Unknown Command(0x%02X) %04x %04x %04x %04x %04x\n", instruction, ygr_cxt.regs.HIRQ, ygr_cxt.regs.CR1, ygr_cxt.regs.CR2, ygr_cxt.regs.CR3, ygr_cxt.regs.CR4);
750 break;
751 }
752 }
753 #else
754 #define ygr_a_bus_cd_cmd_log()
755 #endif
756
757 //////////////////////////////////////////////////////////////////////////////
758
ygr_a_bus_write_word(u32 addr,u16 val)759 void FASTCALL ygr_a_bus_write_word(u32 addr, u16 val) {
760
761 if ((addr & 0x7FFF) <= 0xFFF)
762 {
763 addr &= 0x3F;
764
765 switch (addr) {
766 case 0x00:
767 if (ygr_cxt.transfer_ctrl & 1)
768 write_fifo(val);
769 break;
770 case 0x08:
771 case 0x0A:
772 ygr_cxt.regs.HIRQ &= val;
773 return;
774 case 0x0C:
775 case 0x0E:
776 ygr_cxt.regs.HIRQMASK = val;
777 return;
778 case 0x18:
779 case 0x1A:
780 ygr_cxt.regs.CR1 = val;
781 return;
782 case 0x1C:
783 case 0x1E:
784 ygr_cxt.regs.CR2 = val;
785 return;
786 case 0x20:
787 case 0x22:
788 ygr_cxt.regs.CR3 = val;
789 return;
790 case 0x24:
791 case 0x26:
792 ygr_cxt.regs.CR4 = val;
793 SH2SendInterrupt(SH1, 70, (sh1_cxt.onchip.intc.iprb >> 4) & 0xf);
794 ygr_a_bus_cd_cmd_log();
795 return;
796 case 0x28:
797 case 0x2A:
798 ygr_cxt.regs.MPEGRGB = val;
799 return;
800 default:
801 LOG("ygr\t:Undocumented register write %08X\n", addr);
802 break;
803 }
804 }
805 }
806
807 //////////////////////////////////////////////////////////////////////////////
808
ygr_a_bus_read_long(u32 addr)809 u32 FASTCALL ygr_a_bus_read_long(u32 addr) {
810 u32 val = 0;
811
812 if ((addr & 0x7FFF) <= 0xFFF)
813 {
814 addr &= 0x3F;
815
816 switch (addr) {
817 case 0x00:
818 {
819 u32 top;
820 top = read_fifo();
821 #ifdef ENABLE_TSUNAMI
822 tsunami_log_value("SH2_R_FIFO", top & 0xffff, 16);
823 #endif
824 top <<= 16;
825 top |= read_fifo();
826 #ifdef ENABLE_TSUNAMI
827 tsunami_log_value("SH2_R_FIFO", top & 0xffff, 16);
828 #endif
829 make_fifo_log(top);
830 verify_fifo_log(top);
831 return top;
832 }
833 case 0x08:
834 return ((ygr_cxt.regs.HIRQ << 16) | ygr_cxt.regs.HIRQ);
835 case 0x0C:
836 return ((ygr_cxt.regs.HIRQMASK << 16) | ygr_cxt.regs.HIRQMASK);
837 case 0x18:
838 return ((ygr_cxt.regs.RR1 << 16) | ygr_cxt.regs.RR1);
839 case 0x1C:
840 return ((ygr_cxt.regs.RR2 << 16) | ygr_cxt.regs.RR2);
841 case 0x20:
842 return ((ygr_cxt.regs.RR3 << 16) | ygr_cxt.regs.RR3);
843 case 0x24:
844 ygr_cxt.mbx_status |= 2;
845 return ((ygr_cxt.regs.RR4 << 16) | ygr_cxt.regs.RR4);
846 case 0x28:
847 return ((ygr_cxt.regs.MPEGRGB << 16) | ygr_cxt.regs.MPEGRGB);
848 default:
849 LOG("ygr\t: Undocumented register read %08X\n", addr);
850 break;
851 }
852 }
853 return val;
854 }
855
856 //////////////////////////////////////////////////////////////////////////////
857
ygr_a_bus_write_long(UNUSED u32 addr,UNUSED u32 val)858 void FASTCALL ygr_a_bus_write_long(UNUSED u32 addr, UNUSED u32 val) {
859
860 if ((addr & 0x7FFF) <= 0xFFF)
861 {
862 addr &= 0x3F;
863
864 switch (addr)
865 {
866 case 0x00:
867 if (ygr_cxt.transfer_ctrl & 1)
868 {
869 write_fifo(val >> 16);
870 write_fifo(val);
871 }
872 break;
873 case 0x0c:
874 ygr_cxt.regs.HIRQMASK = val;//gets truncated
875 break;
876 case 0x18000:
877 // transfer data
878 break;
879 default:
880 LOG("ygr\t: Undocumented register write %08X\n", addr);
881 // T3WriteLong(Cs2Area->mem, addr, val);
882 break;
883 }
884 }
885 }
886
sh2_ygr_a_bus_read_word(SH2_struct * sh,u32 addr)887 u16 FASTCALL sh2_ygr_a_bus_read_word(SH2_struct * sh, u32 addr) {
888 return ygr_a_bus_read_word(addr);
889 }
890
sh2_ygr_a_bus_write_word(SH2_struct * sh,u32 addr,u16 val)891 void FASTCALL sh2_ygr_a_bus_write_word(SH2_struct * sh, u32 addr, u16 val) {
892 ygr_a_bus_write_word(addr, val);
893 }
894
sh2_ygr_a_bus_read_long(SH2_struct * sh,u32 addr)895 u32 FASTCALL sh2_ygr_a_bus_read_long(SH2_struct * sh, u32 addr) {
896 return ygr_a_bus_read_long(addr);
897 }
898
sh2_ygr_a_bus_write_long(SH2_struct * sh,UNUSED u32 addr,UNUSED u32 val)899 void FASTCALL sh2_ygr_a_bus_write_long(SH2_struct * sh, UNUSED u32 addr, UNUSED u32 val) {
900 ygr_a_bus_write_long(addr, val);
901 }
902
ygr_cd_irq(u8 flags)903 void ygr_cd_irq(u8 flags)
904 {
905 ygr_cxt.cdirq_flags |= flags;
906 if (ygr_cxt.cdirq_flags & ygr_cxt.regs.HIRQMASK)
907 SH2SendInterrupt(SH1, 71, sh1_cxt.onchip.intc.iprb & 0xf);
908 }
909