1 /*
2 * UAE - The Un*x Amiga Emulator
3 *
4 * AutoConfig (tm) Expansions (ZorroII/III)
5 *
6 * Copyright 1996,1997 Stefan Reinauer <stepan@linux.de>
7 * Copyright 1997 Brian King <Brian_King@Mitel.com>
8 * - added gfxcard code
9 *
10 */
11
12 //#define EXP_DEBUG
13
14 #include "sysconfig.h"
15 #include "sysdeps.h"
16
17 #include "options.h"
18 #include "uae.h"
19 #include "memory_uae.h"
20 #include "rommgr.h"
21 #include "autoconf.h"
22 #include "custom.h"
23 #include "newcpu.h"
24 #include "savestate.h"
25 #include "zfile.h"
26 #include "catweasel.h"
27 #include "cdtv.h"
28 #include "a2091.h"
29 #include "a2065.h"
30 #include "cd32_fmv.h"
31 #include "ncr_scsi.h"
32 #include "debug.h"
33 #include "gayle.h"
34
35 #define MAX_EXPANSION_BOARDS 8
36
37 /* ********************************************************** */
38 /* 00 / 02 */
39 /* er_Type */
40
41 #define Z2_MEM_8MB 0x00 /* Size of Memory Block */
42 #define Z2_MEM_4MB 0x07
43 #define Z2_MEM_2MB 0x06
44 #define Z2_MEM_1MB 0x05
45 #define Z2_MEM_512KB 0x04
46 #define Z2_MEM_256KB 0x03
47 #define Z2_MEM_128KB 0x02
48 #define Z2_MEM_64KB 0x01
49 /* extended definitions */
50 #define Z3_MEM_16MB 0x00
51 #define Z3_MEM_32MB 0x01
52 #define Z3_MEM_64MB 0x02
53 #define Z3_MEM_128MB 0x03
54 #define Z3_MEM_256MB 0x04
55 #define Z3_MEM_512MB 0x05
56 #define Z3_MEM_1GB 0x06
57
58 #define chainedconfig 0x08 /* Next config is part of the same card */
59 #define rom_card 0x10 /* ROM vector is valid */
60 #define add_memory 0x20 /* Link RAM into free memory list */
61
62 #define zorroII 0xc0 /* Type of Expansion Card */
63 #define zorroIII 0x80
64
65 /* ********************************************************** */
66 /* 04 - 06 & 10-16 */
67
68 /* Manufacturer */
69 #define commodore_g 513 /* Commodore Braunschweig (Germany) */
70 #define commodore 514 /* Commodore West Chester */
71 #define gvp 2017 /* GVP */
72 #define ass 2102 /* Advanced Systems & Software */
73 #define hackers_id 2011 /* Special ID for test cards */
74
75 /* Card Type */
76 #define commodore_a2091 3 /* A2091 / A590 Card from C= */
77 #define commodore_a2091_ram 10 /* A2091 / A590 Ram on HD-Card */
78 #define commodore_a2232 70 /* A2232 Multiport Expansion */
79 #define ass_nexus_scsi 1 /* Nexus SCSI Controller */
80
81 #define gvp_series_2_scsi 11
82 #define gvp_iv_24_gfx 32
83
84 /* ********************************************************** */
85 /* 08 - 0A */
86 /* er_Flags */
87 #define Z3_SS_MEM_SAME 0x00
88 #define Z3_SS_MEM_AUTO 0x01
89 #define Z3_SS_MEM_64KB 0x02
90 #define Z3_SS_MEM_128KB 0x03
91 #define Z3_SS_MEM_256KB 0x04
92 #define Z3_SS_MEM_512KB 0x05
93 #define Z3_SS_MEM_1MB 0x06 /* Zorro III card subsize */
94 #define Z3_SS_MEM_2MB 0x07
95 #define Z3_SS_MEM_4MB 0x08
96 #define Z3_SS_MEM_6MB 0x09
97 #define Z3_SS_MEM_8MB 0x0a
98 #define Z3_SS_MEM_10MB 0x0b
99 #define Z3_SS_MEM_12MB 0x0c
100 #define Z3_SS_MEM_14MB 0x0d
101 #define Z3_SS_MEM_defunct1 0x0e
102 #define Z3_SS_MEM_defunct2 0x0f
103
104 #define force_z3 0x10 /* *MUST* be set if card is Z3 */
105 #define ext_size 0x20 /* Use extended size table for bits 0-2 of er_Type */
106 #define no_shutup 0x40 /* Card cannot receive Shut_up_forever */
107 #define care_addr 0x80 /* Z2=Adress HAS to be $200000-$9fffff Z3=1->mem,0=io */
108
109 /* ********************************************************** */
110 /* 40-42 */
111 /* ec_interrupt (unused) */
112
113 #define enable_irq 0x01 /* enable Interrupt */
114 #define reset_card 0x04 /* Reset of Expansion Card - must be 0 */
115 #define card_int2 0x10 /* READ ONLY: IRQ 2 active */
116 #define card_irq6 0x20 /* READ ONLY: IRQ 6 active */
117 #define card_irq7 0x40 /* READ ONLY: IRQ 7 active */
118 #define does_irq 0x80 /* READ ONLY: Card currently throws IRQ */
119
120 /* ********************************************************** */
121
122 /* ROM defines (DiagVec) */
123
124 #define rom_4bit (0x00<<14) /* ROM width */
125 #define rom_8bit (0x01<<14)
126 #define rom_16bit (0x02<<14)
127
128 #define rom_never (0x00<<12) /* Never run Boot Code */
129 #define rom_install (0x01<<12) /* run code at install time */
130 #define rom_binddrv (0x02<<12) /* run code with binddrivers */
131
132 uaecptr ROM_filesys_resname, ROM_filesys_resid;
133 uaecptr ROM_filesys_diagentry;
134 uaecptr ROM_hardfile_resname, ROM_hardfile_resid;
135 uaecptr ROM_hardfile_init;
136 bool uae_boot_rom;
137 int uae_boot_rom_size; /* size = code size only */
138 static bool chipdone;
139
140 /* ********************************************************** */
141
142 static void (*card_init[MAX_EXPANSION_BOARDS]) (void);
143 static void (*card_map[MAX_EXPANSION_BOARDS]) (void);
144 static TCHAR *card_name[MAX_EXPANSION_BOARDS];
145
146 static int ecard, cardno, z3num;
147
148 static uae_u16 uae_id;
149
150 /* ********************************************************** */
151
152 /* Please note: ZorroIII implementation seems to work different
153 * than described in the HRM. This claims that ZorroIII config
154 * address is 0xff000000 while the ZorroII config space starts
155 * at 0x00e80000. In reality, both, Z2 and Z3 cards are
156 * configured in the ZorroII config space. Kickstart 3.1 doesn't
157 * even do a single read or write access to the ZorroIII space.
158 * The original Amiga include files tell the same as the HRM.
159 * ZorroIII: If you set ext_size in er_Flags and give a Z2-size
160 * in er_Type you can very likely add some ZorroII address space
161 * to a ZorroIII card on a real Amiga. This is not implemented
162 * yet.
163 * -- Stefan
164 *
165 * Surprising that 0xFF000000 isn't used. Maybe it depends on the
166 * ROM. Anyway, the HRM says that Z3 cards may appear in Z2 config
167 * space, so what we are doing here is correct.
168 * -- Bernd
169 */
170
171 /* Autoconfig address space at 0xE80000 */
172 static uae_u8 expamem[65536];
173
174 static uae_u8 expamem_lo;
175 static uae_u16 expamem_hi;
176
177 /* Ugly hack for >2M chip RAM in single pool
178 * We can't add it any later or early boot menu
179 * stops working because it sets kicktag at the end
180 * of chip ram...
181 */
addextrachip(uae_u32 sysbase)182 static void addextrachip (uae_u32 sysbase)
183 {
184 if (currprefs.chipmem_size <= 0x00200000)
185 return;
186 if (sysbase & 0x80000001)
187 return;
188 if (!valid_address (sysbase, 1000))
189 return;
190 uae_u32 ml = get_long (sysbase + 322);
191 if (!valid_address (ml, 32))
192 return;
193 uae_u32 next;
194 while ((next = get_long (ml))) {
195 if (!valid_address (ml, 32))
196 return;
197 uae_u32 upper = get_long (ml + 24);
198 uae_u32 lower = get_long (ml + 20);
199 if (lower & ~0xffff) {
200 ml = next;
201 continue;
202 }
203 uae_u16 attr = get_word (ml + 14);
204 if ((attr & 0x8002) != 2) {
205 ml = next;
206 continue;
207 }
208 if (upper >= currprefs.chipmem_size)
209 return;
210 uae_u32 added = currprefs.chipmem_size - upper;
211 uae_u32 first = get_long (ml + 16);
212 put_long (ml + 24, currprefs.chipmem_size); // mh_Upper
213 put_long (ml + 28, get_long (ml + 28) + added); // mh_Free
214 uae_u32 next;
215 while (first) {
216 next = first;
217 first = get_long (next);
218 }
219 uae_u32 bytes = get_long (next + 4);
220 if (next + bytes == 0x00200000) {
221 put_long (next + 4, currprefs.chipmem_size - next);
222 } else {
223 put_long (0x00200000 + 0, 0);
224 put_long (0x00200000 + 4, added);
225 put_long (next, 0x00200000);
226 }
227 return;
228 }
229 }
230
231
232 static uae_u32 REGPARAM3 expamem_lget (uaecptr) REGPARAM;
233 static uae_u32 REGPARAM3 expamem_wget (uaecptr) REGPARAM;
234 static uae_u32 REGPARAM3 expamem_bget (uaecptr) REGPARAM;
235 static void REGPARAM3 expamem_lput (uaecptr, uae_u32) REGPARAM;
236 static void REGPARAM3 expamem_wput (uaecptr, uae_u32) REGPARAM;
237 static void REGPARAM3 expamem_bput (uaecptr, uae_u32) REGPARAM;
238
239 void p96memstart (void);
240
241 addrbank expamem_bank = {
242 expamem_lget, expamem_wget, expamem_bget,
243 expamem_lput, expamem_wput, expamem_bput,
244 default_xlate, default_check, NULL, _T("Autoconfig"),
245 dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE
246 };
247
expamem_map_clear(void)248 static void expamem_map_clear (void)
249 {
250 write_log (_T("expamem_map_clear() got called. Shouldn't happen.\n"));
251 }
252
expamem_init_clear(void)253 static void expamem_init_clear (void)
254 {
255 memset (expamem, 0xff, sizeof expamem);
256 }
257 /* autoconfig area is "non-existing" after last device */
expamem_init_clear_zero(void)258 static void expamem_init_clear_zero (void)
259 {
260 map_banks (&dummy_bank, 0xe8, 1, 0);
261 }
262
expamem_init_clear2(void)263 static void expamem_init_clear2 (void)
264 {
265 expamem_bank.name = _T("Autoconfig");
266 expamem_init_clear_zero ();
267 ecard = cardno;
268 }
269
expamem_init_last(void)270 static void expamem_init_last (void)
271 {
272 expamem_init_clear2 ();
273 write_log (_T("Memory map after autoconfig:\n"));
274 memory_map_dump();
275 }
276
expamem_next(void)277 void expamem_next (void)
278 {
279 expamem_init_clear ();
280 map_banks (&expamem_bank, 0xE8, 1, 0);
281 ++ecard;
282 if (ecard < cardno) {
283 expamem_bank.name = card_name[ecard] ? card_name[ecard] : (TCHAR*) _T("None");
284 (*card_init[ecard]) ();
285 } else {
286 expamem_init_clear2 ();
287 }
288 }
289
expamem_lget(uaecptr addr)290 static uae_u32 REGPARAM2 expamem_lget (uaecptr addr)
291 {
292 write_log (_T("warning: READ.L from address $%lx PC=%x\n"), addr, M68K_GETPC);
293 return (expamem_wget (addr) << 16) | expamem_wget (addr + 2);
294 }
295
expamem_wget(uaecptr addr)296 static uae_u32 REGPARAM2 expamem_wget (uaecptr addr)
297 {
298 uae_u32 v = (expamem_bget (addr) << 8) | expamem_bget (addr + 1);
299 write_log (_T("warning: READ.W from address $%lx=%04x PC=%x\n"), addr, v & 0xffff, M68K_GETPC);
300 return v;
301 }
302
expamem_bget(uaecptr addr)303 static uae_u32 REGPARAM2 expamem_bget (uaecptr addr)
304 {
305 uae_u8 b;
306 #ifdef JIT
307 special_mem |= S_READ;
308 #endif
309 if (!chipdone) {
310 chipdone = true;
311 addextrachip (get_long (4));
312 }
313 addr &= 0xFFFF;
314 b = expamem[addr];
315 #ifdef EXP_DEBUG
316 write_log (_T("expamem_bget %x %x\n"), addr, b);
317 #endif
318 return b;
319 }
320
expamem_write(uaecptr addr,uae_u32 value)321 static void REGPARAM2 expamem_write (uaecptr addr, uae_u32 value)
322 {
323 #ifdef JIT
324 special_mem |= S_WRITE;
325 #endif
326 addr &= 0xffff;
327 if (addr == 00 || addr == 02 || addr == 0x40 || addr == 0x42) {
328 expamem[addr] = (value & 0xf0);
329 expamem[addr + 2] = (value & 0x0f) << 4;
330 } else {
331 expamem[addr] = ~(value & 0xf0);
332 expamem[addr + 2] = ~((value & 0x0f) << 4);
333 }
334 }
335
expamem_type(void)336 static int REGPARAM2 expamem_type (void)
337 {
338 return ((expamem[0] | expamem[2] >> 4) & 0xc0);
339 }
340
expamem_lput(uaecptr addr,uae_u32 value)341 static void REGPARAM2 expamem_lput (uaecptr addr, uae_u32 value)
342 {
343 #ifdef JIT
344 special_mem |= S_WRITE;
345 #endif
346 write_log (_T("warning: WRITE.L to address $%lx : value $%lx\n"), addr, value);
347 }
348
expamem_wput(uaecptr addr,uae_u32 value)349 static void REGPARAM2 expamem_wput (uaecptr addr, uae_u32 value)
350 {
351 #ifdef EXP_DEBUG
352 write_log (_T("expamem_wput %x %x\n"), addr, value);
353 #endif
354 #ifdef JIT
355 special_mem |= S_WRITE;
356 #endif
357 value &= 0xffff;
358 if (ecard >= cardno)
359 return;
360 if (expamem_type() != zorroIII)
361 write_log (_T("warning: WRITE.W to address $%lx : value $%x\n"), addr, value);
362 else {
363 switch (addr & 0xff) {
364 case 0x44:
365 if (expamem_type() == zorroIII) {
366 uae_u32 p1, p2 = 0;
367 // +Bernd Roesch & Toni Wilen
368 p1 = get_word (regs.regs[11] + 0x20);
369 if (expamem[0] & add_memory) {
370 // Z3 RAM expansion
371 p2 = 0;
372 while (!p2 && z3num < 2) {
373 if (z3num == 0 && currprefs.z3fastmem_size)
374 p2 = z3fastmem_start >> 16;
375 else if (z3num == 1 && currprefs.z3fastmem2_size)
376 p2 = z3fastmem2_start >> 16;
377 if (!p2)
378 z3num++;
379 }
380 z3num++;
381 } else {
382 // Z3 P96 RAM
383 if (p96ram_start & 0xff000000)
384 p2 = p96ram_start >> 16;
385 }
386 put_word (regs.regs[11] + 0x20, p2);
387 put_word (regs.regs[11] + 0x28, p2);
388 // -Bernd Roesch
389 expamem_hi = p2;
390 (*card_map[ecard]) ();
391 if (p1 != p2)
392 write_log (_T(" Card %d remapped %04x0000 -> %04x0000\n"), ecard + 1, p1, p2);
393 write_log (_T(" Card %d (Zorro%s) done.\n"), ecard + 1, expamem_type () == 0xc0 ? _T("II") : _T("III"));
394 expamem_next ();
395 }
396 break;
397 case 0x4c:
398 write_log (_T(" Card %d (Zorro%s) had no success.\n"), ecard + 1, expamem_type () == 0xc0 ? _T("II") : _T("III"));
399 expamem_hi = expamem_lo = 0;
400 (*card_map[ecard]) ();
401 break;
402 }
403 }
404 }
405
expamem_bput(uaecptr addr,uae_u32 value)406 static void REGPARAM2 expamem_bput (uaecptr addr, uae_u32 value)
407 {
408 #ifdef EXP_DEBUG
409 write_log (_T("expamem_bput %x %x\n"), addr, value);
410 #endif
411 #ifdef JIT
412 special_mem |= S_WRITE;
413 #endif
414 if (ecard >= cardno)
415 return;
416 value &= 0xff;
417 switch (addr & 0xff) {
418 case 0x30:
419 case 0x32:
420 expamem_hi = 0;
421 expamem_lo = 0;
422 expamem_write (0x48, 0x00);
423 break;
424
425 case 0x48:
426 if (expamem_type () == zorroII) {
427 expamem_hi = value;
428 (*card_map[ecard]) ();
429 write_log (_T(" Card %d (Zorro%s) done.\n"), ecard + 1, expamem_type () == 0xc0 ? _T("II") : _T("III"));
430 expamem_next ();
431 } else if (expamem_type() == zorroIII)
432 expamem_lo = value;
433 break;
434
435 case 0x4a:
436 if (expamem_type () == zorroII)
437 expamem_lo = value;
438 break;
439
440 case 0x4c:
441 expamem_hi = expamem_lo = 0;
442 (*card_map[ecard]) ();
443 write_log (_T(" Card %d (Zorro%s) had no success.\n"), ecard + 1, expamem_type () == 0xc0 ? _T("II") : _T("III"));
444 expamem_next ();
445 break;
446 }
447 }
448
449 #ifdef CD32
450
expamem_map_cd32fmv(void)451 static void expamem_map_cd32fmv (void)
452 {
453 uaecptr start = ((expamem_hi | (expamem_lo >> 4)) << 16);
454 cd32_fmv_init (start);
455 }
456
expamem_init_cd32fmv(void)457 static void expamem_init_cd32fmv (void)
458 {
459 int ids[] = { 23, -1 };
460 struct romlist *rl = getromlistbyids (ids);
461 struct romdata *rd;
462 struct zfile *z;
463
464 expamem_init_clear ();
465 if (!rl)
466 return;
467 write_log (_T("CD32 FMV ROM '%s' %d.%d\n"), rl->path, rl->rd->ver, rl->rd->rev);
468 rd = rl->rd;
469 z = read_rom (&rd);
470 if (z) {
471 zfile_fread (expamem, 128, 1, z);
472 zfile_fclose (z);
473 }
474 }
475
476 #endif
477
478 /* ********************************************************** */
479
480 /*
481 * Fast Memory
482 */
483
484 static uae_u32 fastmem_mask;
485
486 static uae_u32 REGPARAM3 fastmem_lget (uaecptr) REGPARAM;
487 static uae_u32 REGPARAM3 fastmem_wget (uaecptr) REGPARAM;
488 static uae_u32 REGPARAM3 fastmem_bget (uaecptr) REGPARAM;
489 static void REGPARAM3 fastmem_lput (uaecptr, uae_u32) REGPARAM;
490 static void REGPARAM3 fastmem_wput (uaecptr, uae_u32) REGPARAM;
491 static void REGPARAM3 fastmem_bput (uaecptr, uae_u32) REGPARAM;
492 static int REGPARAM3 fastmem_check (uaecptr addr, uae_u32 size) REGPARAM;
493 static uae_u8 *REGPARAM3 fastmem_xlate (uaecptr addr) REGPARAM;
494
495 uaecptr fastmem_start; /* Determined by the OS */
496 static uae_u8 *fastmemory;
497
fastmem_lget(uaecptr addr)498 static uae_u32 REGPARAM2 fastmem_lget (uaecptr addr)
499 {
500 uae_u8 *m;
501 addr -= fastmem_start & fastmem_mask;
502 addr &= fastmem_mask;
503 m = fastmemory + addr;
504 return do_get_mem_long ((uae_u32 *)m);
505 }
506
fastmem_wget(uaecptr addr)507 static uae_u32 REGPARAM2 fastmem_wget (uaecptr addr)
508 {
509 uae_u8 *m;
510 addr -= fastmem_start & fastmem_mask;
511 addr &= fastmem_mask;
512 m = fastmemory + addr;
513 return do_get_mem_word ((uae_u16 *)m);
514 }
515
fastmem_bget(uaecptr addr)516 static uae_u32 REGPARAM2 fastmem_bget (uaecptr addr)
517 {
518 addr -= fastmem_start & fastmem_mask;
519 addr &= fastmem_mask;
520 return fastmemory[addr];
521 }
522
fastmem_lput(uaecptr addr,uae_u32 l)523 static void REGPARAM2 fastmem_lput (uaecptr addr, uae_u32 l)
524 {
525 uae_u8 *m;
526 addr -= fastmem_start & fastmem_mask;
527 addr &= fastmem_mask;
528 m = fastmemory + addr;
529 do_put_mem_long ((uae_u32 *)m, l);
530 }
531
fastmem_wput(uaecptr addr,uae_u32 w)532 static void REGPARAM2 fastmem_wput (uaecptr addr, uae_u32 w)
533 {
534 uae_u8 *m;
535 addr -= fastmem_start & fastmem_mask;
536 addr &= fastmem_mask;
537 m = fastmemory + addr;
538 do_put_mem_word ((uae_u16 *)m, w);
539 }
540
fastmem_bput(uaecptr addr,uae_u32 b)541 static void REGPARAM2 fastmem_bput (uaecptr addr, uae_u32 b)
542 {
543 addr -= fastmem_start & fastmem_mask;
544 addr &= fastmem_mask;
545 fastmemory[addr] = b;
546 }
547
fastmem_check(uaecptr addr,uae_u32 size)548 static int REGPARAM2 fastmem_check (uaecptr addr, uae_u32 size)
549 {
550 addr -= fastmem_start & fastmem_mask;
551 addr &= fastmem_mask;
552 return (addr + size) <= allocated_fastmem;
553 }
554
fastmem_xlate(uaecptr addr)555 static uae_u8 *REGPARAM2 fastmem_xlate (uaecptr addr)
556 {
557 addr -= fastmem_start & fastmem_mask;
558 addr &= fastmem_mask;
559 return fastmemory + addr;
560 }
561
562 addrbank fastmem_bank = {
563 fastmem_lget, fastmem_wget, fastmem_bget,
564 fastmem_lput, fastmem_wput, fastmem_bput,
565 fastmem_xlate, fastmem_check, NULL, _T("Fast memory"),
566 fastmem_lget, fastmem_wget, ABFLAG_RAM
567 };
568
569
570 #ifdef CATWEASEL
571
572 /*
573 * Catweasel ZorroII
574 */
575
576 static uae_u32 REGPARAM3 catweasel_lget (uaecptr) REGPARAM;
577 static uae_u32 REGPARAM3 catweasel_wget (uaecptr) REGPARAM;
578 static uae_u32 REGPARAM3 catweasel_bget (uaecptr) REGPARAM;
579 static void REGPARAM3 catweasel_lput (uaecptr, uae_u32) REGPARAM;
580 static void REGPARAM3 catweasel_wput (uaecptr, uae_u32) REGPARAM;
581 static void REGPARAM3 catweasel_bput (uaecptr, uae_u32) REGPARAM;
582 static int REGPARAM3 catweasel_check (uaecptr addr, uae_u32 size) REGPARAM;
583 static uae_u8 *REGPARAM3 catweasel_xlate (uaecptr addr) REGPARAM;
584
585 static uae_u32 catweasel_mask;
586 static uae_u32 catweasel_start;
587
catweasel_lget(uaecptr addr)588 static uae_u32 REGPARAM2 catweasel_lget (uaecptr addr)
589 {
590 #ifdef JIT
591 special_mem |= S_READ;
592 #endif
593 write_log (_T("catweasel_lget @%08X!\n"),addr);
594 return 0;
595 }
596
catweasel_wget(uaecptr addr)597 static uae_u32 REGPARAM2 catweasel_wget (uaecptr addr)
598 {
599 #ifdef JIT
600 special_mem |= S_READ;
601 #endif
602 write_log (_T("catweasel_wget @%08X!\n"),addr);
603 return 0;
604 }
605
catweasel_bget(uaecptr addr)606 static uae_u32 REGPARAM2 catweasel_bget (uaecptr addr)
607 {
608 #ifdef JIT
609 special_mem |= S_READ;
610 #endif
611 addr -= catweasel_start & catweasel_mask;
612 addr &= catweasel_mask;
613 return catweasel_do_bget (addr);
614 }
615
catweasel_lput(uaecptr addr,uae_u32 l)616 static void REGPARAM2 catweasel_lput (uaecptr addr, uae_u32 l)
617 {
618 #ifdef JIT
619 special_mem |= S_WRITE;
620 #endif
621 write_log (_T("catweasel_lput @%08X=%08X!\n"),addr,l);
622 }
623
catweasel_wput(uaecptr addr,uae_u32 w)624 static void REGPARAM2 catweasel_wput (uaecptr addr, uae_u32 w)
625 {
626 #ifdef JIT
627 special_mem |= S_WRITE;
628 #endif
629 write_log (_T("catweasel_wput @%08X=%04X!\n"),addr,w);
630 }
631
catweasel_bput(uaecptr addr,uae_u32 b)632 static void REGPARAM2 catweasel_bput (uaecptr addr, uae_u32 b)
633 {
634 #ifdef JIT
635 special_mem |= S_WRITE;
636 #endif
637 addr -= catweasel_start & catweasel_mask;
638 addr &= catweasel_mask;
639 catweasel_do_bput (addr, b);
640 }
641
catweasel_check(uaecptr addr,uae_u32 size)642 static int REGPARAM2 catweasel_check (uaecptr addr, uae_u32 size)
643 {
644 return 0;
645 }
646
catweasel_xlate(uaecptr addr)647 static uae_u8 *REGPARAM2 catweasel_xlate (uaecptr addr)
648 {
649 write_log (_T("catweasel_xlate @%08X size %08X\n"), addr);
650 return 0;
651 }
652
653 static addrbank catweasel_bank = {
654 catweasel_lget, catweasel_wget, catweasel_bget,
655 catweasel_lput, catweasel_wput, catweasel_bput,
656 catweasel_xlate, catweasel_check, NULL, _T("Catweasel"),
657 dummy_lgeti, dummy_wgeti, ABFLAG_IO
658 };
659
expamem_map_catweasel(void)660 static void expamem_map_catweasel (void)
661 {
662 catweasel_start = ((expamem_hi | (expamem_lo >> 4)) << 16);
663 if (catweasel_start) {
664 map_banks (&catweasel_bank, catweasel_start >> 16, 1, 0);
665 write_log (_T("Catweasel MK%d: mapped @$%lx\n"), cwc.type, catweasel_start);
666 }
667 }
668
expamem_init_catweasel(void)669 static void expamem_init_catweasel (void)
670 {
671 uae_u8 productid = cwc.type >= CATWEASEL_TYPE_MK3 ? 66 : 200;
672 uae_u16 vendorid = cwc.type >= CATWEASEL_TYPE_MK3 ? 4626 : 5001;
673
674 catweasel_mask = (cwc.type >= CATWEASEL_TYPE_MK3) ? 0xffff : 0x1ffff;
675
676 expamem_init_clear ();
677
678 expamem_write (0x00, (cwc.type >= CATWEASEL_TYPE_MK3 ? Z2_MEM_64KB : Z2_MEM_128KB) | zorroII);
679
680 expamem_write (0x04, productid);
681
682 expamem_write (0x08, 0);
683
684 expamem_write (0x10, vendorid >> 8);
685 expamem_write (0x14, vendorid & 0xff);
686
687 expamem_write (0x18, 0x00); /* ser.no. Byte 0 */
688 expamem_write (0x1c, 0x00); /* ser.no. Byte 1 */
689 expamem_write (0x20, 0x00); /* ser.no. Byte 2 */
690 expamem_write (0x24, 0x00); /* ser.no. Byte 3 */
691
692 expamem_write (0x28, 0x00); /* Rom-Offset hi */
693 expamem_write (0x2c, 0x00); /* ROM-Offset lo */
694
695 expamem_write (0x40, 0x00); /* Ctrl/Statusreg.*/
696 }
697
698 #endif
699
700 #ifdef FILESYS
701
702 /*
703 * Filesystem device ROM
704 * This is very simple, the Amiga shouldn't be doing things with it.
705 */
706
707 static uae_u32 REGPARAM3 filesys_lget (uaecptr) REGPARAM;
708 static uae_u32 REGPARAM3 filesys_wget (uaecptr) REGPARAM;
709 static uae_u32 REGPARAM3 filesys_bget (uaecptr) REGPARAM;
710 static void REGPARAM3 filesys_lput (uaecptr, uae_u32) REGPARAM;
711 static void REGPARAM3 filesys_wput (uaecptr, uae_u32) REGPARAM;
712 static void REGPARAM3 filesys_bput (uaecptr, uae_u32) REGPARAM;
713
714 static uae_u32 filesys_start; /* Determined by the OS */
715 uae_u8 *filesysory;
716
filesys_lget(uaecptr addr)717 static uae_u32 REGPARAM2 filesys_lget (uaecptr addr)
718 {
719 uae_u8 *m;
720 #ifdef JIT
721 special_mem |= S_READ;
722 #endif
723 addr -= filesys_start & 65535;
724 addr &= 65535;
725 m = filesysory + addr;
726 #ifdef EXP_DEBUG
727 write_log (_T("filesys_lget %x %x\n"), addr, do_get_mem_long ((uae_u32 *)m));
728 #endif
729 return do_get_mem_long ((uae_u32 *)m);
730 }
731
filesys_wget(uaecptr addr)732 static uae_u32 REGPARAM2 filesys_wget (uaecptr addr)
733 {
734 uae_u8 *m;
735 #ifdef JIT
736 special_mem |= S_READ;
737 #endif
738 addr -= filesys_start & 65535;
739 addr &= 65535;
740 m = filesysory + addr;
741 #ifdef EXP_DEBUG
742 write_log (_T("filesys_wget %x %x\n"), addr, do_get_mem_word ((uae_u16 *)m));
743 #endif
744 return do_get_mem_word ((uae_u16 *)m);
745 }
746
filesys_bget(uaecptr addr)747 static uae_u32 REGPARAM2 filesys_bget (uaecptr addr)
748 {
749 #ifdef JIT
750 special_mem |= S_READ;
751 #endif
752 addr -= filesys_start & 65535;
753 addr &= 65535;
754 #ifdef EXP_DEBUG
755 write_log (_T("filesys_bget %x %x\n"), addr, filesysory[addr]);
756 #endif
757 return filesysory[addr];
758 }
759
filesys_lput(uaecptr addr,uae_u32 l)760 static void REGPARAM2 filesys_lput (uaecptr addr, uae_u32 l)
761 {
762 #ifdef JIT
763 special_mem |= S_WRITE;
764 #endif
765 write_log (_T("filesys_lput called PC=%p\n"), M68K_GETPC);
766 }
767
filesys_wput(uaecptr addr,uae_u32 w)768 static void REGPARAM2 filesys_wput (uaecptr addr, uae_u32 w)
769 {
770 #ifdef JIT
771 special_mem |= S_WRITE;
772 #endif
773 write_log (_T("filesys_wput called PC=%p\n"), M68K_GETPC);
774 }
775
filesys_bput(uaecptr addr,uae_u32 b)776 static void REGPARAM2 filesys_bput (uaecptr addr, uae_u32 b)
777 {
778 #ifdef JIT
779 special_mem |= S_WRITE;
780 #endif
781 #ifdef EXP_DEBUG
782 write_log (_T("filesys_bput %x %x\n"), addr, b);
783 #endif
784 }
785
786 static addrbank filesys_bank = {
787 filesys_lget, filesys_wget, filesys_bget,
788 filesys_lput, filesys_wput, filesys_bput,
789 default_xlate, default_check, NULL, _T("Filesystem Autoconfig Area"),
790 dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE
791 };
792
793 #endif /* FILESYS */
794
795 /*
796 * Z3fastmem Memory
797 */
798
799 static uae_u32 z3fastmem_mask, z3fastmem2_mask, z3chipmem_mask;
800 uaecptr z3fastmem_start, z3fastmem2_start, z3chipmem_start;
801 static uae_u8 *z3fastmem, *z3fastmem2, *z3chipmem;
802
z3fastmem_lget(uaecptr addr)803 static uae_u32 REGPARAM2 z3fastmem_lget (uaecptr addr)
804 {
805 uae_u8 *m;
806 addr -= z3fastmem_start & z3fastmem_mask;
807 addr &= z3fastmem_mask;
808 m = z3fastmem + addr;
809 return do_get_mem_long ((uae_u32 *)m);
810 }
z3fastmem_wget(uaecptr addr)811 static uae_u32 REGPARAM2 z3fastmem_wget (uaecptr addr)
812 {
813 uae_u8 *m;
814 addr -= z3fastmem_start & z3fastmem_mask;
815 addr &= z3fastmem_mask;
816 m = z3fastmem + addr;
817 return do_get_mem_word ((uae_u16 *)m);
818 }
819
z3fastmem_bget(uaecptr addr)820 static uae_u32 REGPARAM2 z3fastmem_bget (uaecptr addr)
821 {
822 addr -= z3fastmem_start & z3fastmem_mask;
823 addr &= z3fastmem_mask;
824 return z3fastmem[addr];
825 }
z3fastmem_lput(uaecptr addr,uae_u32 l)826 static void REGPARAM2 z3fastmem_lput (uaecptr addr, uae_u32 l)
827 {
828 uae_u8 *m;
829 addr -= z3fastmem_start & z3fastmem_mask;
830 addr &= z3fastmem_mask;
831 m = z3fastmem + addr;
832 do_put_mem_long ((uae_u32 *)m, l);
833 }
z3fastmem_wput(uaecptr addr,uae_u32 w)834 static void REGPARAM2 z3fastmem_wput (uaecptr addr, uae_u32 w)
835 {
836 uae_u8 *m;
837 addr -= z3fastmem_start & z3fastmem_mask;
838 addr &= z3fastmem_mask;
839 m = z3fastmem + addr;
840 do_put_mem_word ((uae_u16 *)m, w);
841 }
z3fastmem_bput(uaecptr addr,uae_u32 b)842 static void REGPARAM2 z3fastmem_bput (uaecptr addr, uae_u32 b)
843 {
844 addr -= z3fastmem_start & z3fastmem_mask;
845 addr &= z3fastmem_mask;
846 z3fastmem[addr] = b;
847 }
z3fastmem_check(uaecptr addr,uae_u32 size)848 static int REGPARAM2 z3fastmem_check (uaecptr addr, uae_u32 size)
849 {
850 addr -= z3fastmem_start & z3fastmem_mask;
851 addr &= z3fastmem_mask;
852 return (addr + size) <= allocated_z3fastmem;
853 }
z3fastmem_xlate(uaecptr addr)854 static uae_u8 *REGPARAM2 z3fastmem_xlate (uaecptr addr)
855 {
856 addr -= z3fastmem_start & z3fastmem_mask;
857 addr &= z3fastmem_mask;
858 return z3fastmem + addr;
859 }
860
z3fastmem2_lget(uaecptr addr)861 static uae_u32 REGPARAM2 z3fastmem2_lget (uaecptr addr)
862 {
863 uae_u8 *m;
864 addr -= z3fastmem2_start & z3fastmem2_mask;
865 addr &= z3fastmem2_mask;
866 m = z3fastmem2 + addr;
867 return do_get_mem_long ((uae_u32 *)m);
868 }
z3fastmem2_wget(uaecptr addr)869 static uae_u32 REGPARAM2 z3fastmem2_wget (uaecptr addr)
870 {
871 uae_u8 *m;
872 addr -= z3fastmem2_start & z3fastmem2_mask;
873 addr &= z3fastmem2_mask;
874 m = z3fastmem2 + addr;
875 return do_get_mem_word ((uae_u16 *)m);
876 }
z3fastmem2_bget(uaecptr addr)877 static uae_u32 REGPARAM2 z3fastmem2_bget (uaecptr addr)
878 {
879 addr -= z3fastmem2_start & z3fastmem2_mask;
880 addr &= z3fastmem2_mask;
881 return z3fastmem2[addr];
882 }
z3fastmem2_lput(uaecptr addr,uae_u32 l)883 static void REGPARAM2 z3fastmem2_lput (uaecptr addr, uae_u32 l)
884 {
885 uae_u8 *m;
886 addr -= z3fastmem2_start & z3fastmem2_mask;
887 addr &= z3fastmem2_mask;
888 m = z3fastmem2 + addr;
889 do_put_mem_long ((uae_u32 *)m, l);
890 }
z3fastmem2_wput(uaecptr addr,uae_u32 w)891 static void REGPARAM2 z3fastmem2_wput (uaecptr addr, uae_u32 w)
892 {
893 uae_u8 *m;
894 addr -= z3fastmem2_start & z3fastmem2_mask;
895 addr &= z3fastmem2_mask;
896 m = z3fastmem2 + addr;
897 do_put_mem_word ((uae_u16 *)m, w);
898 }
z3fastmem2_bput(uaecptr addr,uae_u32 b)899 static void REGPARAM2 z3fastmem2_bput (uaecptr addr, uae_u32 b)
900 {
901 addr -= z3fastmem2_start & z3fastmem2_mask;
902 addr &= z3fastmem2_mask;
903 z3fastmem2[addr] = b;
904 }
z3fastmem2_check(uaecptr addr,uae_u32 size)905 static int REGPARAM2 z3fastmem2_check (uaecptr addr, uae_u32 size)
906 {
907 addr -= z3fastmem2_start & z3fastmem2_mask;
908 addr &= z3fastmem2_mask;
909 return (addr + size) <= allocated_z3fastmem2;
910 }
z3fastmem2_xlate(uaecptr addr)911 static uae_u8 *REGPARAM2 z3fastmem2_xlate (uaecptr addr)
912 {
913 addr -= z3fastmem2_start & z3fastmem2_mask;
914 addr &= z3fastmem2_mask;
915 return z3fastmem2 + addr;
916 }
917
z3chipmem_lget(uaecptr addr)918 static uae_u32 REGPARAM2 z3chipmem_lget (uaecptr addr)
919 {
920 uae_u8 *m;
921 addr -= z3chipmem_start & z3chipmem_mask;
922 addr &= z3chipmem_mask;
923 m = z3chipmem + addr;
924 return do_get_mem_long ((uae_u32 *)m);
925 }
z3chipmem_wget(uaecptr addr)926 static uae_u32 REGPARAM2 z3chipmem_wget (uaecptr addr)
927 {
928 uae_u8 *m;
929 addr -= z3chipmem_start & z3chipmem_mask;
930 addr &= z3chipmem_mask;
931 m = z3chipmem + addr;
932 return do_get_mem_word ((uae_u16 *)m);
933 }
z3chipmem_bget(uaecptr addr)934 static uae_u32 REGPARAM2 z3chipmem_bget (uaecptr addr)
935 {
936 addr -= z3chipmem_start & z3chipmem_mask;
937 addr &= z3chipmem_mask;
938 return z3chipmem[addr];
939 }
z3chipmem_lput(uaecptr addr,uae_u32 l)940 static void REGPARAM2 z3chipmem_lput (uaecptr addr, uae_u32 l)
941 {
942 uae_u8 *m;
943 addr -= z3chipmem_start & z3chipmem_mask;
944 addr &= z3chipmem_mask;
945 m = z3chipmem + addr;
946 do_put_mem_long ((uae_u32 *)m, l);
947 }
z3chipmem_wput(uaecptr addr,uae_u32 w)948 static void REGPARAM2 z3chipmem_wput (uaecptr addr, uae_u32 w)
949 {
950 uae_u8 *m;
951 addr -= z3chipmem_start & z3chipmem_mask;
952 addr &= z3chipmem_mask;
953 m = z3chipmem + addr;
954 do_put_mem_word ((uae_u16 *)m, w);
955 }
z3chipmem_bput(uaecptr addr,uae_u32 b)956 static void REGPARAM2 z3chipmem_bput (uaecptr addr, uae_u32 b)
957 {
958 addr -= z3chipmem_start & z3chipmem_mask;
959 addr &= z3chipmem_mask;
960 z3chipmem[addr] = b;
961 }
z3chipmem_check(uaecptr addr,uae_u32 size)962 static int REGPARAM2 z3chipmem_check (uaecptr addr, uae_u32 size)
963 {
964 addr -= z3chipmem_start & z3chipmem_mask;
965 addr &= z3chipmem_mask;
966 return (addr + size) <= allocated_z3chipmem;
967 }
z3chipmem_xlate(uaecptr addr)968 static uae_u8 *REGPARAM2 z3chipmem_xlate (uaecptr addr)
969 {
970 addr -= z3chipmem_start & z3chipmem_mask;
971 addr &= z3chipmem_mask;
972 return z3chipmem + addr;
973 }
974
975
976 addrbank z3fastmem_bank = {
977 z3fastmem_lget, z3fastmem_wget, z3fastmem_bget,
978 z3fastmem_lput, z3fastmem_wput, z3fastmem_bput,
979 z3fastmem_xlate, z3fastmem_check, NULL, _T("ZorroIII Fast RAM"),
980 z3fastmem_lget, z3fastmem_wget, ABFLAG_RAM
981 };
982 addrbank z3fastmem2_bank = {
983 z3fastmem2_lget, z3fastmem2_wget, z3fastmem2_bget,
984 z3fastmem2_lput, z3fastmem2_wput, z3fastmem2_bput,
985 z3fastmem2_xlate, z3fastmem2_check, NULL, _T("ZorroIII Fast RAM #2"),
986 z3fastmem2_lget, z3fastmem2_wget, ABFLAG_RAM
987 };
988 addrbank z3chipmem_bank = {
989 z3chipmem_lget, z3chipmem_wget, z3chipmem_bget,
990 z3chipmem_lput, z3chipmem_wput, z3chipmem_bput,
991 z3chipmem_xlate, z3chipmem_check, NULL, _T("MegaChipRAM"),
992 z3chipmem_lget, z3chipmem_wget, ABFLAG_RAM
993 };
994
995 /* Z3-based UAEGFX-card */
996 uae_u32 gfxmem_mask; /* for memory.c */
997 uae_u8 *gfxmemory;
998 uae_u32 gfxmem_start;
999
1000 /* ********************************************************** */
1001
1002 /*
1003 * Expansion Card (ZORRO II) for 1/2/4/8 MB of Fast Memory
1004 */
1005
expamem_map_fastcard(void)1006 static void expamem_map_fastcard (void)
1007 {
1008 fastmem_start = ((expamem_hi | (expamem_lo >> 4)) << 16);
1009 if (fastmem_start) {
1010 map_banks (&fastmem_bank, fastmem_start >> 16, allocated_fastmem >> 16, 0);
1011 write_log (_T("Fastcard: mapped @$%lx: %dMB fast memory\n"), fastmem_start, allocated_fastmem >> 20);
1012 }
1013 }
1014
expamem_init_fastcard(void)1015 static void expamem_init_fastcard (void)
1016 {
1017 uae_u16 mid = (currprefs.cs_a2091 || currprefs.uae_hide) ? commodore : uae_id;
1018 uae_u8 pid = (currprefs.cs_a2091 || currprefs.uae_hide) ? commodore_a2091_ram : (currprefs.maprom ? 1 : 81);
1019
1020 expamem_init_clear ();
1021 if (allocated_fastmem == 0x100000)
1022 expamem_write (0x00, Z2_MEM_1MB + add_memory + zorroII);
1023 else if (allocated_fastmem == 0x200000)
1024 expamem_write (0x00, Z2_MEM_2MB + add_memory + zorroII);
1025 else if (allocated_fastmem == 0x400000)
1026 expamem_write (0x00, Z2_MEM_4MB + add_memory + zorroII);
1027 else if (allocated_fastmem == 0x800000)
1028 expamem_write (0x00, Z2_MEM_8MB + add_memory + zorroII);
1029
1030 expamem_write (0x08, care_addr);
1031
1032 expamem_write (0x04, pid);
1033
1034 expamem_write (0x10, mid >> 8);
1035 expamem_write (0x14, mid & 0xff);
1036
1037 expamem_write (0x18, 0x00); /* ser.no. Byte 0 */
1038 expamem_write (0x1c, 0x00); /* ser.no. Byte 1 */
1039 expamem_write (0x20, 0x00); /* ser.no. Byte 2 */
1040 expamem_write (0x24, 0x01); /* ser.no. Byte 3 */
1041
1042 expamem_write (0x28, 0x00); /* Rom-Offset hi */
1043 expamem_write (0x2c, 0x00); /* ROM-Offset lo */
1044
1045 expamem_write (0x40, 0x00); /* Ctrl/Statusreg.*/
1046 }
1047
1048 /* ********************************************************** */
1049
1050 #ifdef FILESYS
1051
1052 /*
1053 * Filesystem device
1054 */
1055
expamem_map_filesys(void)1056 static void expamem_map_filesys (void)
1057 {
1058 uaecptr a;
1059
1060 filesys_start = ((expamem_hi | (expamem_lo >> 4)) << 16);
1061 map_banks (&filesys_bank, filesys_start >> 16, 1, 0);
1062 write_log (_T("Filesystem: mapped memory @$%lx.\n"), filesys_start);
1063 /* 68k code needs to know this. */
1064 a = here ();
1065 org (rtarea_base + RTAREA_FSBOARD);
1066 dl (filesys_start + 0x2000);
1067 org (a);
1068 }
1069
expamem_init_filesys(void)1070 static void expamem_init_filesys (void)
1071 {
1072 /* struct DiagArea - the size has to be large enough to store several device ROMTags */
1073 uae_u8 diagarea[] = { 0x90, 0x00, /* da_Config, da_Flags */
1074 0x02, 0x00, /* da_Size */
1075 0x01, 0x00, /* da_DiagPoint */
1076 0x01, 0x06 /* da_BootPoint */
1077 };
1078
1079 expamem_init_clear ();
1080 expamem_write (0x00, Z2_MEM_64KB | rom_card | zorroII);
1081
1082 expamem_write (0x08, no_shutup);
1083
1084 expamem_write (0x04, currprefs.maprom ? 2 : 82);
1085 expamem_write (0x10, uae_id >> 8);
1086 expamem_write (0x14, uae_id & 0xff);
1087
1088 expamem_write (0x18, 0x00); /* ser.no. Byte 0 */
1089 expamem_write (0x1c, 0x00); /* ser.no. Byte 1 */
1090 expamem_write (0x20, 0x00); /* ser.no. Byte 2 */
1091 expamem_write (0x24, 0x01); /* ser.no. Byte 3 */
1092
1093 /* er_InitDiagVec */
1094 expamem_write (0x28, 0x10); /* Rom-Offset hi */
1095 expamem_write (0x2c, 0x00); /* ROM-Offset lo */
1096
1097 expamem_write (0x40, 0x00); /* Ctrl/Statusreg.*/
1098
1099 /* Build a DiagArea */
1100 memcpy (expamem + 0x1000, diagarea, sizeof diagarea);
1101
1102 /* Call DiagEntry */
1103 do_put_mem_word ((uae_u16 *)(expamem + 0x1100), 0x4EF9); /* JMP */
1104 do_put_mem_long ((uae_u32 *)(expamem + 0x1102), ROM_filesys_diagentry);
1105
1106 /* What comes next is a plain bootblock */
1107 do_put_mem_word ((uae_u16 *)(expamem + 0x1106), 0x4EF9); /* JMP */
1108 do_put_mem_long ((uae_u32 *)(expamem + 0x1108), EXPANSION_bootcode);
1109
1110 memcpy (filesysory, expamem, 0x3000);
1111 }
1112
1113 #endif
1114
1115 /*
1116 * Zorro III expansion memory
1117 */
1118
expamem_map_z3fastmem_2(addrbank * bank,uaecptr * startp,uae_u32 size,uae_u32 allocated,int chip)1119 static void expamem_map_z3fastmem_2 (addrbank *bank, uaecptr *startp, uae_u32 size, uae_u32 allocated, int chip)
1120 {
1121 int z3fs = ((expamem_hi | (expamem_lo >> 4)) << 16);
1122 int start = *startp;
1123
1124 if (z3fs) {
1125 if (start != z3fs) {
1126 write_log (_T("WARNING: Z3MEM mapping changed from $%08x to $%08x\n"), start, z3fs);
1127 map_banks (&dummy_bank, start >> 16, size >> 16, allocated);
1128 *startp = z3fs;
1129 map_banks (bank, start >> 16, size >> 16, allocated);
1130 }
1131 write_log (_T("Z3MEM (32bit): mapped @$%08x: %d MB Zorro III %s memory \n"),
1132 start, allocated / 0x100000, chip ? _T("chip") : _T("fast"));
1133 }
1134 }
1135
expamem_map_z3fastmem(void)1136 static void expamem_map_z3fastmem (void)
1137 {
1138 expamem_map_z3fastmem_2 (&z3fastmem_bank, &z3fastmem_start, currprefs.z3fastmem_size, allocated_z3fastmem, 0);
1139 }
expamem_map_z3fastmem2(void)1140 static void expamem_map_z3fastmem2 (void)
1141 {
1142 expamem_map_z3fastmem_2 (&z3fastmem2_bank, &z3fastmem2_start, currprefs.z3fastmem2_size, allocated_z3fastmem2, 0);
1143 }
1144
expamem_init_z3fastmem_2(addrbank * bank,uae_u32 start,uae_u32 size,uae_u32 allocated)1145 static void expamem_init_z3fastmem_2 (addrbank *bank, uae_u32 start, uae_u32 size, uae_u32 allocated)
1146 {
1147 int code = (allocated == 0x100000 ? Z2_MEM_1MB
1148 : allocated == 0x200000 ? Z2_MEM_2MB
1149 : allocated == 0x400000 ? Z2_MEM_4MB
1150 : allocated == 0x800000 ? Z2_MEM_8MB
1151 : allocated == 0x1000000 ? Z3_MEM_16MB
1152 : allocated == 0x2000000 ? Z3_MEM_32MB
1153 : allocated == 0x4000000 ? Z3_MEM_64MB
1154 : allocated == 0x8000000 ? Z3_MEM_128MB
1155 : allocated == 0x10000000 ? Z3_MEM_256MB
1156 : allocated == 0x20000000 ? Z3_MEM_512MB
1157 : Z3_MEM_1GB);
1158 int subsize = (allocated == 0x100000 ? Z3_SS_MEM_1MB
1159 : allocated == 0x200000 ? Z3_SS_MEM_2MB
1160 : allocated == 0x400000 ? Z3_SS_MEM_4MB
1161 : allocated == 0x800000 ? Z3_SS_MEM_8MB
1162 : Z3_SS_MEM_SAME);
1163
1164 if (allocated < 0x1000000)
1165 code = Z3_MEM_16MB; /* Z3 physical board size is always at least 16M */
1166
1167 expamem_init_clear ();
1168 expamem_write (0x00, add_memory | zorroIII | code);
1169
1170 expamem_write (0x08, care_addr | force_z3 | (allocated > 0x800000 ? ext_size : subsize));
1171
1172 expamem_write (0x04, currprefs.maprom ? 3 : 83);
1173
1174 expamem_write (0x10, uae_id >> 8);
1175 expamem_write (0x14, uae_id & 0xff);
1176
1177 expamem_write (0x18, 0x00); /* ser.no. Byte 0 */
1178 expamem_write (0x1c, 0x00); /* ser.no. Byte 1 */
1179 expamem_write (0x20, 0x00); /* ser.no. Byte 2 */
1180 expamem_write (0x24, 0x01); /* ser.no. Byte 3 */
1181
1182 expamem_write (0x28, 0x00); /* Rom-Offset hi */
1183 expamem_write (0x2c, 0x00); /* ROM-Offset lo */
1184
1185 expamem_write (0x40, 0x00); /* Ctrl/Statusreg.*/
1186
1187 map_banks (bank, start >> 16, size >> 16, allocated);
1188
1189 }
expamem_init_z3fastmem(void)1190 static void expamem_init_z3fastmem (void)
1191 {
1192 expamem_init_z3fastmem_2 (&z3fastmem_bank, z3fastmem_start, currprefs.z3fastmem_size, allocated_z3fastmem);
1193 }
expamem_init_z3fastmem2(void)1194 static void expamem_init_z3fastmem2 (void)
1195 {
1196 expamem_init_z3fastmem_2 (&z3fastmem2_bank, z3fastmem2_start, currprefs.z3fastmem2_size, allocated_z3fastmem2);
1197 }
1198
1199 #ifdef __LIBRETRO__
1200 uaecptr p96ram_start;
1201 #endif
1202
1203 #ifdef PICASSO96
1204 /*
1205 * Fake Graphics Card (ZORRO III) - BDK
1206 */
1207
1208 uaecptr p96ram_start;
1209
expamem_map_gfxcard(void)1210 static void expamem_map_gfxcard (void)
1211 {
1212 gfxmem_start = (expamem_hi | (expamem_lo >> 4)) << 16;
1213 if (gfxmem_start) {
1214 map_banks (&gfxmem_bank, gfxmem_start >> 16, allocated_gfxmem >> 16, allocated_gfxmem);
1215 write_log (_T("%sUAEGFX-card: mapped @$%lx, %d MB RTG RAM\n"), currprefs.rtgmem_type ? _T("Z3") : _T("Z2"), gfxmem_start, allocated_gfxmem / 0x100000);
1216 }
1217 }
1218
expamem_init_gfxcard(bool z3)1219 static void expamem_init_gfxcard (bool z3)
1220 {
1221 int code = (allocated_gfxmem == 0x100000 ? Z2_MEM_1MB
1222 : allocated_gfxmem == 0x200000 ? Z2_MEM_2MB
1223 : allocated_gfxmem == 0x400000 ? Z2_MEM_4MB
1224 : allocated_gfxmem == 0x800000 ? Z2_MEM_8MB
1225 : allocated_gfxmem == 0x1000000 ? Z3_MEM_16MB
1226 : allocated_gfxmem == 0x2000000 ? Z3_MEM_32MB
1227 : allocated_gfxmem == 0x4000000 ? Z3_MEM_64MB
1228 : allocated_gfxmem == 0x8000000 ? Z3_MEM_128MB
1229 : allocated_gfxmem == 0x10000000 ? Z3_MEM_256MB
1230 : allocated_gfxmem == 0x20000000 ? Z3_MEM_512MB
1231 : Z3_MEM_1GB);
1232 int subsize = (allocated_gfxmem == 0x100000 ? Z3_SS_MEM_1MB
1233 : allocated_gfxmem == 0x200000 ? Z3_SS_MEM_2MB
1234 : allocated_gfxmem == 0x400000 ? Z3_SS_MEM_4MB
1235 : allocated_gfxmem == 0x800000 ? Z3_SS_MEM_8MB
1236 : Z3_SS_MEM_SAME);
1237
1238 if (allocated_gfxmem < 0x1000000 && z3)
1239 code = Z3_MEM_16MB; /* Z3 physical board size is always at least 16M */
1240
1241 expamem_init_clear ();
1242 expamem_write (0x00, (z3 ? zorroIII : zorroII) | code);
1243
1244 expamem_write (0x08, care_addr | (z3 ? (force_z3 | (allocated_gfxmem > 0x800000 ? ext_size: subsize)) : 0));
1245 expamem_write (0x04, 96);
1246
1247 expamem_write (0x10, uae_id >> 8);
1248 expamem_write (0x14, uae_id & 0xff);
1249
1250 expamem_write (0x18, 0x00); /* ser.no. Byte 0 */
1251 expamem_write (0x1c, 0x00); /* ser.no. Byte 1 */
1252 expamem_write (0x20, 0x00); /* ser.no. Byte 2 */
1253 expamem_write (0x24, 0x01); /* ser.no. Byte 3 */
1254
1255 expamem_write (0x28, 0x00); /* ROM-Offset hi */
1256 expamem_write (0x2c, 0x00); /* ROM-Offset lo */
1257
1258 expamem_write (0x40, 0x00); /* Ctrl/Statusreg.*/
1259 }
expamem_init_gfxcard_z3(void)1260 static void expamem_init_gfxcard_z3 (void)
1261 {
1262 expamem_init_gfxcard (true);
1263 }
expamem_init_gfxcard_z2(void)1264 static void expamem_init_gfxcard_z2 (void)
1265 {
1266 expamem_init_gfxcard (false);
1267 }
1268 #endif
1269
1270
1271 #ifdef SAVESTATE
1272 static size_t fast_filepos, z3_filepos, z3_filepos2, z3_fileposchip, p96_filepos;
1273 #endif
1274
free_fastmemory(void)1275 void free_fastmemory (void)
1276 {
1277 if (fastmemory)
1278 mapped_free (fastmemory);
1279 fastmemory = 0;
1280 }
1281
mapped_malloc_dynamic(uae_u32 * currpsize,uae_u32 * changedpsize,uae_u8 ** memory,uae_u32 * allocated,uae_u32 * mask,int max,const TCHAR * name)1282 static bool mapped_malloc_dynamic (uae_u32 *currpsize, uae_u32 *changedpsize, uae_u8 **memory, uae_u32 *allocated, uae_u32 *mask, int max, const TCHAR *name)
1283 {
1284 int alloc = *currpsize;
1285
1286 *allocated = 0;
1287 *memory = NULL;
1288 *mask = 0;
1289
1290 if (!alloc)
1291 return false;
1292
1293 while (alloc >= max * 1024 * 1024) {
1294 uae_u8 *mem = mapped_malloc (alloc, name);
1295 if (mem) {
1296 *memory = mem;
1297 *currpsize = alloc;
1298 *changedpsize = alloc;
1299 *mask = alloc - 1;
1300 *allocated = alloc;
1301 return true;
1302 }
1303 write_log (_T("Out of memory for %s, %d bytes, %d MB. Will try %d bytes\n"), name, alloc, alloc/0x100000, alloc/2);
1304 alloc /= 2;
1305 }
1306
1307 return false;
1308 }
1309
1310
allocate_expamem(void)1311 static void allocate_expamem (void)
1312 {
1313 currprefs.fastmem_size = changed_prefs.fastmem_size;
1314 currprefs.fastmem2_size = changed_prefs.fastmem2_size;
1315 currprefs.z3fastmem_size = changed_prefs.z3fastmem_size;
1316 currprefs.z3fastmem2_size = changed_prefs.z3fastmem2_size;
1317 currprefs.rtgmem_size = changed_prefs.rtgmem_size;
1318 currprefs.rtgmem_type = changed_prefs.rtgmem_type;
1319 currprefs.z3chipmem_size = changed_prefs.z3chipmem_size;
1320
1321 z3chipmem_start = currprefs.z3fastmem_start;
1322 z3fastmem_start = currprefs.z3fastmem_start;
1323 if (currprefs.z3chipmem_size)
1324 z3fastmem_start += currprefs.z3chipmem_size + 16 * 1024 * 1024;
1325 z3fastmem2_start = z3fastmem_start + currprefs.z3fastmem_size;
1326
1327 if (allocated_fastmem != currprefs.fastmem_size) {
1328 free_fastmemory ();
1329 allocated_fastmem = currprefs.fastmem_size;
1330 fastmem_mask = allocated_fastmem - 1;
1331
1332 if (allocated_fastmem) {
1333 fastmemory = mapped_malloc (allocated_fastmem, _T("fast"));
1334 if (fastmemory == 0) {
1335 write_log (_T("Out of memory for fastmem card.\n"));
1336 allocated_fastmem = 0;
1337 }
1338 }
1339 memory_hardreset (1);
1340 }
1341 if (allocated_z3fastmem != currprefs.z3fastmem_size) {
1342 if (z3fastmem)
1343 mapped_free (z3fastmem);
1344 mapped_malloc_dynamic (&currprefs.z3fastmem_size, &changed_prefs.z3fastmem_size, &z3fastmem, &allocated_z3fastmem, &z3fastmem_mask, 1, _T("z3"));
1345 memory_hardreset (1);
1346 }
1347 if (allocated_z3fastmem2 != currprefs.z3fastmem2_size) {
1348 if (z3fastmem2)
1349 mapped_free (z3fastmem2);
1350 z3fastmem2 = 0;
1351
1352 allocated_z3fastmem2 = currprefs.z3fastmem2_size;
1353 z3fastmem2_mask = allocated_z3fastmem2 - 1;
1354
1355 if (allocated_z3fastmem2) {
1356 z3fastmem2 = mapped_malloc (allocated_z3fastmem2, _T("z3_2"));
1357 if (z3fastmem2 == 0) {
1358 write_log (_T("Out of memory for 32 bit fast memory #2.\n"));
1359 allocated_z3fastmem2 = 0;
1360 }
1361 }
1362 memory_hardreset (1);
1363 }
1364 if (allocated_z3chipmem != currprefs.z3chipmem_size) {
1365 if (z3chipmem)
1366 mapped_free (z3chipmem);
1367 mapped_malloc_dynamic (&currprefs.z3chipmem_size, &changed_prefs.z3chipmem_size, &z3chipmem, &allocated_z3chipmem, &z3chipmem_mask, 16, _T("z3_chip"));
1368 memory_hardreset (1);
1369 }
1370
1371 #ifdef PICASSO96
1372 if (allocated_gfxmem != currprefs.rtgmem_size) {
1373 if (gfxmemory)
1374 mapped_free (gfxmemory);
1375 mapped_malloc_dynamic (&currprefs.rtgmem_size, &changed_prefs.rtgmem_size, &gfxmemory, &allocated_gfxmem, &gfxmem_mask, 1, currprefs.rtgmem_type ? _T("z3_gfx") : _T("z2_gfx"));
1376 memory_hardreset (1);
1377 }
1378 #endif
1379
1380 z3fastmem_bank.baseaddr = z3fastmem;
1381 z3fastmem2_bank.baseaddr = z3fastmem2;
1382 z3chipmem_bank.baseaddr = z3chipmem;
1383 fastmem_bank.baseaddr = fastmemory;
1384 #ifdef PICASSO96
1385 gfxmem_bank.baseaddr = gfxmemory;
1386 #endif
1387
1388 #ifdef SAVESTATE
1389 if (savestate_state == STATE_RESTORE) {
1390 if (allocated_fastmem > 0) {
1391 restore_ram (fast_filepos, fastmemory);
1392 map_banks (&fastmem_bank, fastmem_start >> 16, currprefs.fastmem_size >> 16,
1393 allocated_fastmem);
1394 }
1395 if (allocated_z3fastmem > 0) {
1396 restore_ram (z3_filepos, z3fastmem);
1397 map_banks (&z3fastmem_bank, z3fastmem_start >> 16, currprefs.z3fastmem_size >> 16,
1398 allocated_z3fastmem);
1399 }
1400 if (allocated_z3fastmem2 > 0) {
1401 restore_ram (z3_filepos2, z3fastmem2);
1402 map_banks (&z3fastmem2_bank, z3fastmem2_start >> 16, currprefs.z3fastmem2_size >> 16,
1403 allocated_z3fastmem2);
1404 }
1405 if (allocated_z3chipmem > 0) {
1406 restore_ram (z3_fileposchip, z3chipmem);
1407 map_banks (&z3chipmem_bank, z3chipmem_start >> 16, currprefs.z3chipmem_size >> 16,
1408 allocated_z3fastmem2);
1409 }
1410 #ifdef PICASSO96
1411 if (allocated_gfxmem > 0 && gfxmem_start > 0) {
1412 restore_ram (p96_filepos, gfxmemory);
1413 map_banks (&gfxmem_bank, gfxmem_start >> 16, currprefs.rtgmem_size >> 16,
1414 allocated_gfxmem);
1415 }
1416 #endif
1417 }
1418 #endif /* SAVESTATE */
1419 }
1420
check_boot_rom(void)1421 static uaecptr check_boot_rom (void)
1422 {
1423 uaecptr b = RTAREA_DEFAULT;
1424 addrbank *ab;
1425
1426 if (currprefs.cs_cdtvcd || currprefs.cs_cdtvscsi || currprefs.uae_hide > 1)
1427 b = RTAREA_BACKUP;
1428 if (currprefs.cs_mbdmac == 1)
1429 b = RTAREA_BACKUP;
1430 ab = &get_mem_bank (RTAREA_DEFAULT);
1431 if (ab) {
1432 if (valid_address (RTAREA_DEFAULT, 65536))
1433 b = RTAREA_BACKUP;
1434 }
1435 if (nr_directory_units (NULL))
1436 return b;
1437 if (nr_directory_units (&currprefs))
1438 return b;
1439 if (currprefs.socket_emu)
1440 return b;
1441 if (currprefs.uaeserial)
1442 return b;
1443 if (currprefs.scsi == 1)
1444 return b;
1445 if (currprefs.sana2)
1446 return b;
1447 if (currprefs.input_tablet > 0)
1448 return b;
1449 if (currprefs.rtgmem_size)
1450 return b;
1451 if (currprefs.chipmem_size > 2 * 1024 * 1024)
1452 return b;
1453 if (currprefs.z3chipmem_size)
1454 return b;
1455 return 0;
1456 }
1457
need_uae_boot_rom(void)1458 uaecptr need_uae_boot_rom (void)
1459 {
1460 uaecptr v;
1461
1462 uae_boot_rom = 0;
1463 v = check_boot_rom ();
1464 if (v)
1465 uae_boot_rom = 1;
1466 if (!rtarea_base) {
1467 uae_boot_rom = 0;
1468 v = 0;
1469 }
1470 return v;
1471 }
1472
expamem_init_a2065(void)1473 static void expamem_init_a2065 (void)
1474 {
1475 #ifdef A2065
1476 a2065_init ();
1477 #endif
1478 }
expamem_init_cdtv(void)1479 static void expamem_init_cdtv (void)
1480 {
1481 #ifdef CDTV
1482 cdtv_init ();
1483 #endif
1484 }
expamem_init_a2091(void)1485 static void expamem_init_a2091 (void)
1486 {
1487 #ifdef A2091
1488 a2091_init ();
1489 #endif
1490 }
expamem_init_a4091(void)1491 static void expamem_init_a4091 (void)
1492 {
1493 #ifdef NCR
1494 ncr_init ();
1495 #endif
1496 }
1497
p96memstart(void)1498 void p96memstart (void)
1499 {
1500 /* make sure there is always empty space between Z3 and P96 RAM */
1501 p96ram_start = currprefs.z3fastmem_start + ((currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size + 0xffffff) & ~0xffffff);
1502 if (p96ram_start == currprefs.z3fastmem_start + currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size &&
1503 (currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size < 512 * 1024 * 1024 || currprefs.rtgmem_size < 128 * 1024 * 1024))
1504 p96ram_start += 0x1000000;
1505 }
1506
expamem_reset(void)1507 void expamem_reset (void)
1508 {
1509 int do_mount = 1;
1510
1511 ecard = 0;
1512 cardno = 0;
1513 chipdone = false;
1514
1515 if (currprefs.uae_hide)
1516 uae_id = commodore;
1517 else
1518 uae_id = hackers_id;
1519
1520 allocate_expamem ();
1521 expamem_bank.name = _T("Autoconfig [reset]");
1522
1523 /* check if Kickstart version is below 1.3 */
1524 if (kickstart_version && do_mount
1525 && (/* Kickstart 1.0 & 1.1! */
1526 kickstart_version == 0xFFFF
1527 /* Kickstart < 1.3 */
1528 || kickstart_version < 34))
1529 {
1530 /* warn user */
1531 write_log (_T("Kickstart version is below 1.3! Disabling automount devices.\n"));
1532 do_mount = 0;
1533 }
1534 if (need_uae_boot_rom () == 0)
1535 do_mount = 0;
1536 if (fastmemory != NULL && currprefs.chipmem_size <= 2 * 1024 * 1024) {
1537 if (currprefs.fastmem_autoconfig) {
1538 fastmem_bank.name = _T("Fast memory");
1539 card_name[cardno] = _T("Z2Fast");
1540 card_init[cardno] = expamem_init_fastcard;
1541 card_map[cardno++] = expamem_map_fastcard;
1542 } else {
1543 fastmem_bank.name = _T("Fast memory (non-autoconfig)");
1544 map_banks (&fastmem_bank, 0x00200000 >> 16, allocated_fastmem >> 16, 0);
1545 }
1546 }
1547
1548 #ifdef CDTV
1549 if (currprefs.cs_cdtvcd) {
1550 card_name[cardno] = _T("CDTV DMAC");
1551 card_init[cardno] = expamem_init_cdtv;
1552 card_map[cardno++] = NULL;
1553 }
1554 #endif
1555 #ifdef CD32
1556 if (currprefs.cs_cd32cd && currprefs.fastmem_size == 0 && currprefs.chipmem_size <= 0x200000) {
1557 int ids[] = { 23, -1 };
1558 struct romlist *rl = getromlistbyids (ids);
1559 if (rl && !_tcscmp (rl->path, currprefs.cartfile)) {
1560 card_name[cardno] = _T("CD32MPEG");
1561 card_init[cardno] = expamem_init_cd32fmv;
1562 card_map[cardno++] = expamem_map_cd32fmv;
1563 }
1564 }
1565 #endif
1566 #ifdef A2091
1567 if (currprefs.cs_a2091) {
1568 card_name[cardno] = _T("A2091");
1569 card_init[cardno] = expamem_init_a2091;
1570 card_map[cardno++] = NULL;
1571 }
1572 #endif
1573 #ifdef A2065
1574 if (currprefs.a2065name[0]) {
1575 card_name[cardno] = _T("A2065");
1576 card_init[cardno] = expamem_init_a2065;
1577 card_map[cardno++] = NULL;
1578 }
1579 #endif
1580 #ifdef FILESYS
1581 if (do_mount) {
1582 card_name[cardno] = _T("UAEFS");
1583 card_init[cardno] = expamem_init_filesys;
1584 card_map[cardno++] = expamem_map_filesys;
1585 }
1586 #endif
1587 #ifdef CATWEASEL
1588 if (currprefs.catweasel && catweasel_init ()) {
1589 card_name[cardno] = _T("CWMK2");
1590 card_init[cardno] = expamem_init_catweasel;
1591 card_map[cardno++] = expamem_map_catweasel;
1592 }
1593 #endif
1594 #ifdef PICASSO96
1595 if (!currprefs.rtgmem_type && gfxmemory != NULL) {
1596 card_name[cardno] = _T("Z2RTG");
1597 card_init[cardno] = expamem_init_gfxcard_z2;
1598 card_map[cardno++] = expamem_map_gfxcard;
1599 }
1600 #endif
1601
1602 /* Z3 boards last */
1603
1604 if (z3fastmem != NULL) {
1605 z3num = 0;
1606 card_name[cardno] = _T("Z3Fast");
1607 card_init[cardno] = expamem_init_z3fastmem;
1608 card_map[cardno++] = expamem_map_z3fastmem;
1609 map_banks (&z3fastmem_bank, z3fastmem_start >> 16, currprefs.z3fastmem_size >> 16, allocated_z3fastmem);
1610 if (z3fastmem2 != NULL) {
1611 card_name[cardno] = _T("Z3Fast2");
1612 card_init[cardno] = expamem_init_z3fastmem2;
1613 card_map[cardno++] = expamem_map_z3fastmem2;
1614 map_banks (&z3fastmem2_bank, z3fastmem2_start >> 16, currprefs.z3fastmem2_size >> 16, allocated_z3fastmem2);
1615 }
1616 }
1617 if (z3chipmem != NULL)
1618 map_banks (&z3chipmem_bank, z3chipmem_start >> 16, currprefs.z3chipmem_size >> 16, allocated_z3chipmem);
1619 #ifdef NCR
1620 if (currprefs.cs_a4091) {
1621 card_name[cardno] = _T("A4091");
1622 card_init[cardno] = expamem_init_a4091;
1623 card_map[cardno++] = NULL;
1624 }
1625 #endif
1626 #ifdef PICASSO96
1627 if (currprefs.rtgmem_type && gfxmemory != NULL) {
1628 card_name[cardno] = _T("Z3RTG");
1629 card_init[cardno] = expamem_init_gfxcard_z3;
1630 card_map[cardno++] = expamem_map_gfxcard;
1631 }
1632 #endif
1633
1634
1635 if (cardno > 0 && cardno < MAX_EXPANSION_BOARDS) {
1636 card_name[cardno] = _T("Empty");
1637 card_init[cardno] = expamem_init_last;
1638 card_map[cardno++] = expamem_map_clear;
1639 }
1640
1641 if (cardno == 0 || savestate_state)
1642 expamem_init_clear_zero ();
1643 else
1644 (*card_init[0]) ();
1645 }
1646
expansion_init(void)1647 void expansion_init (void)
1648 {
1649 if (savestate_state != STATE_RESTORE) {
1650
1651 allocated_fastmem = 0;
1652 fastmem_mask = fastmem_start = 0;
1653 fastmemory = 0;
1654
1655 #ifdef PICASSO96
1656 allocated_gfxmem = 0;
1657 gfxmem_mask = gfxmem_start = 0;
1658 gfxmemory = 0;
1659 // p96memstart();
1660 #endif
1661
1662 #ifdef CATWEASEL
1663 catweasel_mask = catweasel_start = 0;
1664 #endif
1665
1666 allocated_z3fastmem = 0;
1667 z3fastmem_mask = z3fastmem_start = 0;
1668 z3fastmem = 0;
1669 allocated_z3fastmem2 = 0;
1670 z3fastmem2_mask = z3fastmem2_start = 0;
1671 z3fastmem2 = 0;
1672 allocated_z3chipmem = 0;
1673 z3chipmem_mask = z3chipmem_start = 0;
1674 z3chipmem = 0;
1675 }
1676
1677 #ifdef FILESYS
1678 filesys_start = 0;
1679 filesysory = 0;
1680 #endif
1681
1682 allocate_expamem ();
1683
1684 #ifdef FILESYS
1685 filesysory = mapped_malloc (0x10000, _T("filesys"));
1686 if (!filesysory) {
1687 write_log (_T("virtual memory exhausted (filesysory)!\n"));
1688 exit (0);
1689 }
1690 filesys_bank.baseaddr = filesysory;
1691 #endif
1692 }
1693
expansion_cleanup(void)1694 void expansion_cleanup (void)
1695 {
1696 if (fastmemory)
1697 mapped_free (fastmemory);
1698 fastmemory = 0;
1699
1700 if (z3fastmem)
1701 mapped_free (z3fastmem);
1702 z3fastmem = 0;
1703 if (z3fastmem2)
1704 mapped_free (z3fastmem2);
1705 z3fastmem2 = 0;
1706 if (z3chipmem)
1707 mapped_free (z3chipmem);
1708 z3chipmem = 0;
1709
1710 #ifdef PICASSO96
1711 if (gfxmemory)
1712 mapped_free (gfxmemory);
1713 gfxmemory = 0;
1714 #endif
1715
1716 #ifdef FILESYS
1717 if (filesysory)
1718 mapped_free (filesysory);
1719 filesysory = 0;
1720 #endif
1721
1722 #ifdef CATWEASEL
1723 catweasel_free ();
1724 #endif
1725 }
1726
expansion_clear(void)1727 void expansion_clear (void)
1728 {
1729 if (fastmemory)
1730 memset (fastmemory, 0, allocated_fastmem);
1731 if (z3fastmem)
1732 memset (z3fastmem, 0, allocated_z3fastmem > 0x800000 ? 0x800000 : allocated_z3fastmem);
1733 if (z3fastmem2)
1734 memset (z3fastmem2, 0, allocated_z3fastmem2 > 0x800000 ? 0x800000 : allocated_z3fastmem2);
1735 if (z3chipmem)
1736 memset (z3chipmem, 0, allocated_z3chipmem > 0x800000 ? 0x800000 : allocated_z3chipmem);
1737 if (gfxmemory)
1738 memset (gfxmemory, 0, allocated_gfxmem);
1739 }
1740
1741 #ifdef SAVESTATE
1742
1743 /* State save/restore code. */
1744
save_fram(int * len)1745 uae_u8 *save_fram (int *len)
1746 {
1747 *len = allocated_fastmem;
1748 return fastmemory;
1749 }
1750
save_zram(int * len,int num)1751 uae_u8 *save_zram (int *len, int num)
1752 {
1753 if (num < 0) {
1754 *len = allocated_z3chipmem;
1755 return z3chipmem;
1756 }
1757 *len = num ? allocated_z3fastmem2 : allocated_z3fastmem;
1758 return num ? z3fastmem2 : z3fastmem;
1759 }
1760
save_pram(int * len)1761 uae_u8 *save_pram (int *len)
1762 {
1763 *len = allocated_gfxmem;
1764 return gfxmemory;
1765 }
1766
restore_fram(int len,size_t filepos)1767 void restore_fram (int len, size_t filepos)
1768 {
1769 fast_filepos = filepos;
1770 changed_prefs.fastmem_size = len;
1771 }
1772
restore_zram(int len,size_t filepos,int num)1773 void restore_zram (int len, size_t filepos, int num)
1774 {
1775 if (num == -1) {
1776 z3_fileposchip = filepos;
1777 changed_prefs.z3chipmem_size = len;
1778 } else if (num == 1) {
1779 z3_filepos2 = filepos;
1780 changed_prefs.z3fastmem2_size = len;
1781 } else {
1782 z3_filepos = filepos;
1783 changed_prefs.z3fastmem_size = len;
1784 }
1785 }
1786
restore_pram(int len,size_t filepos)1787 void restore_pram (int len, size_t filepos)
1788 {
1789 p96_filepos = filepos;
1790 changed_prefs.rtgmem_size = len;
1791 }
1792
save_expansion(int * len,uae_u8 * dstptr)1793 uae_u8 *save_expansion (int *len, uae_u8 *dstptr)
1794 {
1795 static uae_u8 t[20];
1796 uae_u8 *dst = t, *dstbak = t;
1797 if (dstptr)
1798 dst = dstbak = dstptr;
1799 save_u32 (fastmem_start);
1800 save_u32 (z3fastmem_start);
1801 save_u32 (gfxmem_start);
1802 save_u32 (rtarea_base);
1803 *len = 4 + 4 + 4 + 4;
1804 return dstbak;
1805 }
1806
restore_expansion(uae_u8 * src)1807 uae_u8 *restore_expansion (uae_u8 *src)
1808 {
1809 fastmem_start = restore_u32 ();
1810 z3fastmem_start = restore_u32 ();
1811 gfxmem_start = restore_u32 ();
1812 rtarea_base = restore_u32 ();
1813 if (rtarea_base != 0 && rtarea_base != RTAREA_DEFAULT && rtarea_base != RTAREA_BACKUP)
1814 rtarea_base = 0;
1815 return src;
1816 }
1817
1818 #endif /* SAVESTATE */
1819