Searched hist:e76f5e73 (Results 1 – 6 of 6) sorted by relevance
| /dragonfly/sys/dev/powermng/clockmod/ |
| H A D | Makefile | e76f5e73 Wed Feb 12 14:15:29 GMT 2014 Sepherosa Ziehau <sephe@dragonflybsd.org> clockmod: Properly implement Intel software controlled clock modulation
Compared w/ the out dated p4tcc code in i386:
- Write the MSR on the correct CPU.
- Fix errata detection.
- Enable 6.25% granularity.
- Fix logical CPU setting by introducing clock modulation domain. Each
domain contains logical CPUs in the same core. When changing duty
cycle we change all logical CPUs' duty cycle in the same domain; mainly
to avoid model specific reaction to logical CPU duty cycle change.
It is controlled through machdep.clockmod_domX.select. Members of the
domain are listed by machdep.clockmod_domX.members. And the available
duty cycles are listed by machdep.clockmod_domX.available.
It is enabled in i386 and x86_64 GENERIC.
* We may want to make powerd(8) aware of clockmod(4)
|
| H A D | clockmod.c | e76f5e73 Wed Feb 12 14:15:29 GMT 2014 Sepherosa Ziehau <sephe@dragonflybsd.org> clockmod: Properly implement Intel software controlled clock modulation
Compared w/ the out dated p4tcc code in i386:
- Write the MSR on the correct CPU.
- Fix errata detection.
- Enable 6.25% granularity.
- Fix logical CPU setting by introducing clock modulation domain. Each
domain contains logical CPUs in the same core. When changing duty
cycle we change all logical CPUs' duty cycle in the same domain; mainly
to avoid model specific reaction to logical CPU duty cycle change.
It is controlled through machdep.clockmod_domX.select. Members of the
domain are listed by machdep.clockmod_domX.members. And the available
duty cycles are listed by machdep.clockmod_domX.available.
It is enabled in i386 and x86_64 GENERIC.
* We may want to make powerd(8) aware of clockmod(4)
|
| /dragonfly/sys/dev/powermng/ |
| H A D | Makefile | diff e76f5e73 Wed Feb 12 14:15:29 GMT 2014 Sepherosa Ziehau <sephe@dragonflybsd.org> clockmod: Properly implement Intel software controlled clock modulation
Compared w/ the out dated p4tcc code in i386:
- Write the MSR on the correct CPU.
- Fix errata detection.
- Enable 6.25% granularity.
- Fix logical CPU setting by introducing clock modulation domain. Each
domain contains logical CPUs in the same core. When changing duty
cycle we change all logical CPUs' duty cycle in the same domain; mainly
to avoid model specific reaction to logical CPU duty cycle change.
It is controlled through machdep.clockmod_domX.select. Members of the
domain are listed by machdep.clockmod_domX.members. And the available
duty cycles are listed by machdep.clockmod_domX.available.
It is enabled in i386 and x86_64 GENERIC.
* We may want to make powerd(8) aware of clockmod(4)
|
| /dragonfly/sys/config/ |
| H A D | X86_64_GENERIC | diff e76f5e73 Wed Feb 12 14:15:29 GMT 2014 Sepherosa Ziehau <sephe@dragonflybsd.org> clockmod: Properly implement Intel software controlled clock modulation
Compared w/ the out dated p4tcc code in i386:
- Write the MSR on the correct CPU.
- Fix errata detection.
- Enable 6.25% granularity.
- Fix logical CPU setting by introducing clock modulation domain. Each
domain contains logical CPUs in the same core. When changing duty
cycle we change all logical CPUs' duty cycle in the same domain; mainly
to avoid model specific reaction to logical CPU duty cycle change.
It is controlled through machdep.clockmod_domX.select. Members of the
domain are listed by machdep.clockmod_domX.members. And the available
duty cycles are listed by machdep.clockmod_domX.available.
It is enabled in i386 and x86_64 GENERIC.
* We may want to make powerd(8) aware of clockmod(4)
|
| H A D | LINT64 | diff e76f5e73 Wed Feb 12 14:15:29 GMT 2014 Sepherosa Ziehau <sephe@dragonflybsd.org> clockmod: Properly implement Intel software controlled clock modulation
Compared w/ the out dated p4tcc code in i386:
- Write the MSR on the correct CPU.
- Fix errata detection.
- Enable 6.25% granularity.
- Fix logical CPU setting by introducing clock modulation domain. Each
domain contains logical CPUs in the same core. When changing duty
cycle we change all logical CPUs' duty cycle in the same domain; mainly
to avoid model specific reaction to logical CPU duty cycle change.
It is controlled through machdep.clockmod_domX.select. Members of the
domain are listed by machdep.clockmod_domX.members. And the available
duty cycles are listed by machdep.clockmod_domX.available.
It is enabled in i386 and x86_64 GENERIC.
* We may want to make powerd(8) aware of clockmod(4)
|
| /dragonfly/sys/conf/ |
| H A D | files | diff e76f5e73 Wed Feb 12 14:15:29 GMT 2014 Sepherosa Ziehau <sephe@dragonflybsd.org> clockmod: Properly implement Intel software controlled clock modulation
Compared w/ the out dated p4tcc code in i386:
- Write the MSR on the correct CPU.
- Fix errata detection.
- Enable 6.25% granularity.
- Fix logical CPU setting by introducing clock modulation domain. Each
domain contains logical CPUs in the same core. When changing duty
cycle we change all logical CPUs' duty cycle in the same domain; mainly
to avoid model specific reaction to logical CPU duty cycle change.
It is controlled through machdep.clockmod_domX.select. Members of the
domain are listed by machdep.clockmod_domX.members. And the available
duty cycles are listed by machdep.clockmod_domX.available.
It is enabled in i386 and x86_64 GENERIC.
* We may want to make powerd(8) aware of clockmod(4)
|