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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/devel/llvm70/llvm-7.0.1.src/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/
H A Dout-of-bounds-indexes.ll8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3
10 ; CHECK-NEXT: ret i32 [[AND1]]
22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3
24 ; CHECK-NEXT: ret i128 [[AND1]]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dload_split_because_of_memsize_or_align359 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
408 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
457 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
506 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
555 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
604 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
653 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
702 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
751 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
800 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-ctpop.mir80 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
81 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
140 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
141 ; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
167 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
168 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
190 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ZEXT]], [[C1]]
191 ; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-ctpop.mir83 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
84 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
145 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
146 ; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
176 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
177 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
202 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
203 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
H A Dlegalize-cttz-zero-undef.mir83 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
84 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
145 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
146 ; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[AND1]](s32)
176 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
177 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
202 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
203 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-ctpop.mir83 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
84 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
145 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
146 ; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
176 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
177 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
202 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
203 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
H A Dlegalize-cttz-zero-undef.mir83 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
84 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
145 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
146 ; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[AND1]](s32)
176 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
177 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
202 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
203 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-ctpop.mir83 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
84 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
146 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
147 ; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
172 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
173 ; CHECK: $vgpr0 = COPY [[AND1]](s32)
198 ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
199 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)

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