| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 184 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
228 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
276 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
332 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | ddr.c | 183 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
227 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
275 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
331 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
|