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Searched refs:CRL_APB_UART0_REF_CTRL (Results 26 – 50 of 72) sorted by relevance

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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/clk/
H A Dclk_zynqmp.c65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) macro
276 return CRL_APB_UART0_REF_CTRL; in zynqmp_clk_get_register()

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