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Searched refs:DDR_ODT_TIMING_LOW_REG (Results 101 – 125 of 186) sorted by relevance

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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rock64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h167 #define DDR_ODT_TIMING_LOW_REG 0x1428 macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training.c1542 if_id, DDR_ODT_TIMING_LOW_REG, in ddr3_tip_freq_set()
1598 DDR_ODT_TIMING_LOW_REG, val, 0xffff0)); in ddr3_tip_write_odt()

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