| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
|
| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
|
| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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