/dports/emulators/qemu42/qemu-4.2.1/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 147 uint64_t Address, const MCRegisterInfo *Decoder); 150 uint64_t Address, const MCRegisterInfo *Decoder); 153 uint64_t Address, const MCRegisterInfo *Decoder); 468 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeINSVE_DF_4() argument 523 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeAddiGroupBranch_4() argument 559 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeDaddiGroupBranch_4() argument 595 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeBlezlGroupBranch_4() argument 867 Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); in DecodeCCRegisterClass() 1030 Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); in DecodeCOP2Mem() 1047 Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); in DecodeCOP3Mem() [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 147 uint64_t Address, const MCRegisterInfo *Decoder); 150 uint64_t Address, const MCRegisterInfo *Decoder); 153 uint64_t Address, const MCRegisterInfo *Decoder); 468 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeINSVE_DF_4() argument 523 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeAddiGroupBranch_4() argument 559 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeDaddiGroupBranch_4() argument 595 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeBlezlGroupBranch_4() argument 867 Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); in DecodeCCRegisterClass() 1030 Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); in DecodeCOP2Mem() 1047 Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); in DecodeCOP3Mem() [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 147 uint64_t Address, const MCRegisterInfo *Decoder); 150 uint64_t Address, const MCRegisterInfo *Decoder); 153 uint64_t Address, const MCRegisterInfo *Decoder); 468 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeINSVE_DF_4() argument 523 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeAddiGroupBranch_4() argument 559 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeDaddiGroupBranch_4() argument 595 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeBlezlGroupBranch_4() argument 867 Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); in DecodeCCRegisterClass() 1030 Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); in DecodeCOP2Mem() 1047 Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); in DecodeCOP3Mem() [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 147 uint64_t Address, const MCRegisterInfo *Decoder); 150 uint64_t Address, const MCRegisterInfo *Decoder); 153 uint64_t Address, const MCRegisterInfo *Decoder); 468 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeINSVE_DF_4() argument 523 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeAddiGroupBranch_4() argument 559 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeDaddiGroupBranch_4() argument 595 uint64_t Address, const MCRegisterInfo *Decoder) in DecodeBlezlGroupBranch_4() argument 867 Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); in DecodeCCRegisterClass() 1030 Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); in DecodeCOP2Mem() 1047 Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); in DecodeCOP3Mem() [all …]
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/dports/devel/capstone4/capstone-4.0.2/arch/Mips/ |
H A D | MipsDisassembler.c | 188 uint64_t Address, const MCRegisterInfo *Decoder); 191 uint64_t Address, MCRegisterInfo *Decoder); 194 uint64_t Address, MCRegisterInfo *Decoder); 197 uint64_t Address, MCRegisterInfo *Decoder); 1331 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); in DecodeSpecial3LlSc() 1663 uint64_t Address, MCRegisterInfo *Decoder) in DecodeSimm9SP() argument 1680 uint64_t Address, MCRegisterInfo *Decoder) in DecodeANDI16Imm() argument 1696 uint64_t Address, MCRegisterInfo *Decoder) in DecodeUImm5lsl2() argument 1727 uint64_t Address, MCRegisterInfo *Decoder) in DecodeRegListOperand16() argument 1743 uint64_t Address, MCRegisterInfo *Decoder) in DecodeMovePRegPair() argument [all …]
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/dports/emulators/qemu/qemu-6.2.0/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 188 uint64_t Address, const MCRegisterInfo *Decoder); 191 uint64_t Address, MCRegisterInfo *Decoder); 194 uint64_t Address, MCRegisterInfo *Decoder); 197 uint64_t Address, MCRegisterInfo *Decoder); 1331 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); in DecodeSpecial3LlSc() 1663 uint64_t Address, MCRegisterInfo *Decoder) in DecodeSimm9SP() argument 1680 uint64_t Address, MCRegisterInfo *Decoder) in DecodeANDI16Imm() argument 1696 uint64_t Address, MCRegisterInfo *Decoder) in DecodeUImm5lsl2() argument 1727 uint64_t Address, MCRegisterInfo *Decoder) in DecodeRegListOperand16() argument 1743 uint64_t Address, MCRegisterInfo *Decoder) in DecodeMovePRegPair() argument [all …]
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/dports/emulators/qemu60/qemu-6.0.0/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 188 uint64_t Address, const MCRegisterInfo *Decoder); 191 uint64_t Address, MCRegisterInfo *Decoder); 194 uint64_t Address, MCRegisterInfo *Decoder); 197 uint64_t Address, MCRegisterInfo *Decoder); 1331 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); in DecodeSpecial3LlSc() 1663 uint64_t Address, MCRegisterInfo *Decoder) in DecodeSimm9SP() argument 1680 uint64_t Address, MCRegisterInfo *Decoder) in DecodeANDI16Imm() argument 1696 uint64_t Address, MCRegisterInfo *Decoder) in DecodeUImm5lsl2() argument 1727 uint64_t Address, MCRegisterInfo *Decoder) in DecodeRegListOperand16() argument 1743 uint64_t Address, MCRegisterInfo *Decoder) in DecodeMovePRegPair() argument [all …]
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/dports/devel/py-capstone/capstone-4.0.1/src/arch/Mips/ |
H A D | MipsDisassembler.c | 187 uint64_t Address, const MCRegisterInfo *Decoder); 190 uint64_t Address, MCRegisterInfo *Decoder); 193 uint64_t Address, MCRegisterInfo *Decoder); 196 uint64_t Address, MCRegisterInfo *Decoder); 1330 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); in DecodeSpecial3LlSc() 1662 uint64_t Address, MCRegisterInfo *Decoder) in DecodeSimm9SP() argument 1679 uint64_t Address, MCRegisterInfo *Decoder) in DecodeANDI16Imm() argument 1695 uint64_t Address, MCRegisterInfo *Decoder) in DecodeUImm5lsl2() argument 1726 uint64_t Address, MCRegisterInfo *Decoder) in DecodeRegListOperand16() argument 1742 uint64_t Address, MCRegisterInfo *Decoder) in DecodeMovePRegPair() argument [all …]
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/dports/emulators/qemu5/qemu-5.2.0/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 188 uint64_t Address, const MCRegisterInfo *Decoder); 191 uint64_t Address, MCRegisterInfo *Decoder); 194 uint64_t Address, MCRegisterInfo *Decoder); 197 uint64_t Address, MCRegisterInfo *Decoder); 1331 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); in DecodeSpecial3LlSc() 1663 uint64_t Address, MCRegisterInfo *Decoder) in DecodeSimm9SP() argument 1680 uint64_t Address, MCRegisterInfo *Decoder) in DecodeANDI16Imm() argument 1696 uint64_t Address, MCRegisterInfo *Decoder) in DecodeUImm5lsl2() argument 1727 uint64_t Address, MCRegisterInfo *Decoder) in DecodeRegListOperand16() argument 1743 uint64_t Address, MCRegisterInfo *Decoder) in DecodeMovePRegPair() argument [all …]
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/dports/devel/redasm/REDasm-2.1.1/LibREDasm/depends/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 187 uint64_t Address, const MCRegisterInfo *Decoder); 190 uint64_t Address, MCRegisterInfo *Decoder); 193 uint64_t Address, MCRegisterInfo *Decoder); 196 uint64_t Address, MCRegisterInfo *Decoder); 1330 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); in DecodeSpecial3LlSc() 1662 uint64_t Address, MCRegisterInfo *Decoder) in DecodeSimm9SP() argument 1679 uint64_t Address, MCRegisterInfo *Decoder) in DecodeANDI16Imm() argument 1695 uint64_t Address, MCRegisterInfo *Decoder) in DecodeUImm5lsl2() argument 1726 uint64_t Address, MCRegisterInfo *Decoder) in DecodeRegListOperand16() argument 1742 uint64_t Address, MCRegisterInfo *Decoder) in DecodeMovePRegPair() argument [all …]
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/dports/devel/xelfviewer/XELFViewer-0.03/XCapstone/3rdparty/Capstone/src/arch/Mips/ |
H A D | MipsDisassembler.c | 188 uint64_t Address, const MCRegisterInfo *Decoder); 191 uint64_t Address, MCRegisterInfo *Decoder); 194 uint64_t Address, MCRegisterInfo *Decoder); 197 uint64_t Address, MCRegisterInfo *Decoder); 1331 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); in DecodeSpecial3LlSc() 1663 uint64_t Address, MCRegisterInfo *Decoder) in DecodeSimm9SP() argument 1680 uint64_t Address, MCRegisterInfo *Decoder) in DecodeANDI16Imm() argument 1696 uint64_t Address, MCRegisterInfo *Decoder) in DecodeUImm5lsl2() argument 1727 uint64_t Address, MCRegisterInfo *Decoder) in DecodeRegListOperand16() argument 1743 uint64_t Address, MCRegisterInfo *Decoder) in DecodeMovePRegPair() argument [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 233 const void *Decoder); 240 const void *Decoder); 1026 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction() 1216 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeSignedLdStInstruction() 1466 Decoder); in DecodeAuthLoadInstruction() 1473 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeAuthLoadInstruction() 1475 DecodeSImm<10>(Inst, offset, Addr, Decoder); in DecodeAuthLoadInstruction() 1620 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); in DecodeModImmTiedInstruction() 1621 DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); in DecodeModImmTiedInstruction() 1641 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeAdrInstruction() [all …]
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/dports/lang/mono/mono-5.10.1.57/mcs/class/Mono.CodeContracts/Mono.CodeContracts.Static.Analysis.Numerical/ |
H A D | GenericExpressionVisitor.cs | 41 Decoder = decoder; in GenericExpressionVisitor() 46 var op = Decoder.OperatorFor (expr); in Visit() 55 … return VisitAnd (Decoder.LeftExpressionFor (expr), Decoder.RightExpressionFor (expr), in Visit() 58 … return VisitOr (Decoder.LeftExpressionFor (expr), Decoder.RightExpressionFor (expr), in Visit() 61 … return VisitXor (Decoder.LeftExpressionFor (expr), Decoder.RightExpressionFor (expr), in Visit() 101 … return VisitModulus (Decoder.LeftExpressionFor (expr), Decoder.RightExpressionFor (expr), in Visit() 237 if (Decoder.IsConstant (expr)) { in TryPolarity() 254 … if (Decoder.IsConstant (left) && Decoder.OperatorFor (right) == ExpressionOperator.Sub) in DispatchCompare() 263 … else if (Decoder.IsConstant (right) && Decoder.OperatorFor (left) == ExpressionOperator.Sub) in DispatchCompare() 280 switch (Decoder.OperatorFor (expr)) { in DispatchVisitNot() [all …]
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/dports/emulators/qemu/qemu-6.2.0/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 43 uint64_t Address, const void *Decoder); 45 uint64_t Address, const void *Decoder); 47 uint64_t Address, const void *Decoder); 129 uint64_t Addr, const void *Decoder); 131 uint64_t Addr, const void *Decoder); 133 uint64_t Addr, const void *Decoder); 135 uint64_t Addr, const void *Decoder); 157 const void *Decoder, int Bits); 279 uint64_t Addr, const void *Decoder) in DecodeFPR128RegisterClass() argument 293 uint64_t Addr, const void *Decoder) in DecodeFPR128_loRegisterClass() argument [all …]
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/dports/emulators/qemu60/qemu-6.0.0/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 43 uint64_t Address, const void *Decoder); 45 uint64_t Address, const void *Decoder); 47 uint64_t Address, const void *Decoder); 129 uint64_t Addr, const void *Decoder); 131 uint64_t Addr, const void *Decoder); 133 uint64_t Addr, const void *Decoder); 135 uint64_t Addr, const void *Decoder); 157 const void *Decoder, int Bits); 279 uint64_t Addr, const void *Decoder) in DecodeFPR128RegisterClass() argument 293 uint64_t Addr, const void *Decoder) in DecodeFPR128_loRegisterClass() argument [all …]
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/dports/emulators/qemu5/qemu-5.2.0/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 43 uint64_t Address, const void *Decoder); 45 uint64_t Address, const void *Decoder); 47 uint64_t Address, const void *Decoder); 129 uint64_t Addr, const void *Decoder); 131 uint64_t Addr, const void *Decoder); 133 uint64_t Addr, const void *Decoder); 135 uint64_t Addr, const void *Decoder); 157 const void *Decoder, int Bits); 279 uint64_t Addr, const void *Decoder) in DecodeFPR128RegisterClass() argument 293 uint64_t Addr, const void *Decoder) in DecodeFPR128_loRegisterClass() argument [all …]
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/dports/devel/xelfviewer/XELFViewer-0.03/XCapstone/3rdparty/Capstone/src/arch/AArch64/ |
H A D | AArch64Disassembler.c | 43 uint64_t Address, const void *Decoder); 45 uint64_t Address, const void *Decoder); 47 uint64_t Address, const void *Decoder); 129 uint64_t Addr, const void *Decoder); 131 uint64_t Addr, const void *Decoder); 133 uint64_t Addr, const void *Decoder); 135 uint64_t Addr, const void *Decoder); 157 const void *Decoder, int Bits); 279 uint64_t Addr, const void *Decoder) in DecodeFPR128RegisterClass() argument 293 uint64_t Addr, const void *Decoder) in DecodeFPR128_loRegisterClass() argument [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 460 const void *Decoder); 470 const void *Decoder); 490 const void *Decoder); 495 const void *Decoder); 500 const void *Decoder); 505 const void *Decoder); 510 const void *Decoder); 515 const void *Decoder); 2278 const void *Decoder) { in DecodeBranchTarget26MM() argument 2524 const void *Decoder) { in DecodeBgtzGroupBranchMMR6() argument [all …]
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 460 const void *Decoder); 470 const void *Decoder); 490 const void *Decoder); 495 const void *Decoder); 500 const void *Decoder); 505 const void *Decoder); 510 const void *Decoder); 515 const void *Decoder); 2284 const void *Decoder) { 2504 const void *Decoder) { [all …]
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/dports/devel/capstone4/capstone-4.0.2/arch/AArch64/ |
H A D | AArch64Disassembler.c | 43 const void *Decoder); 47 const void *Decoder); 50 const void *Decoder); 53 const void *Decoder); 56 const void *Decoder); 59 const void *Decoder); 62 const void *Decoder); 65 const void *Decoder); 68 const void *Decoder); 71 const void *Decoder); [all …]
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/dports/devel/capstone3/capstone-3.0.5/arch/AArch64/ |
H A D | AArch64Disassembler.c | 41 const void *Decoder); 45 const void *Decoder); 48 const void *Decoder); 51 const void *Decoder); 54 const void *Decoder); 57 const void *Decoder); 60 const void *Decoder); 63 const void *Decoder); 66 const void *Decoder); 69 const void *Decoder); [all …]
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/dports/emulators/qemu42/qemu-4.2.1/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 41 const void *Decoder); 45 const void *Decoder); 48 const void *Decoder); 51 const void *Decoder); 54 const void *Decoder); 57 const void *Decoder); 60 const void *Decoder); 63 const void *Decoder); 66 const void *Decoder); 69 const void *Decoder); [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 41 const void *Decoder); 45 const void *Decoder); 48 const void *Decoder); 51 const void *Decoder); 54 const void *Decoder); 57 const void *Decoder); 60 const void *Decoder); 63 const void *Decoder); 66 const void *Decoder); 69 const void *Decoder); [all …]
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/dports/devel/py-capstone/capstone-4.0.1/src/arch/AArch64/ |
H A D | AArch64Disassembler.c | 41 const void *Decoder); 45 const void *Decoder); 48 const void *Decoder); 51 const void *Decoder); 54 const void *Decoder); 57 const void *Decoder); 60 const void *Decoder); 63 const void *Decoder); 66 const void *Decoder); 69 const void *Decoder); [all …]
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/dports/devel/redasm/REDasm-2.1.1/LibREDasm/depends/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 41 const void *Decoder); 45 const void *Decoder); 48 const void *Decoder); 51 const void *Decoder); 54 const void *Decoder); 57 const void *Decoder); 60 const void *Decoder); 63 const void *Decoder); 66 const void *Decoder); 69 const void *Decoder); [all …]
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