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/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc10/gcc-10.3.0/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc8/gcc-8.5.0/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc11/gcc-11.2.0/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
911 ;; (reg:SI FP_REG))
922 [(set (reg:SI FP_REG)
923 (mem:SI (reg:SI FP_REG)))
925 (plus:SI (reg:SI FP_REG)
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/ft32/
H A Dft32.md29 (FP_REG 0)
907 ;; (reg:SI FP_REG))
918 [(set (reg:SI FP_REG)
919 (mem:SI (reg:SI FP_REG)))
921 (plus:SI (reg:SI FP_REG)
/dports/java/openjdk16/jdk16u-jdk-16.0.2-7-1/src/jdk.incubator.foreign/share/classes/jdk/internal/foreign/abi/aarch64/
H A DAArch64VaList.java75 private static final MemoryLayout FP_REG field in AArch64VaList
81 = MemoryLayout.ofSequence(MAX_REGISTER_ARGUMENTS, FP_REG);
84 private static final int FP_SLOT_SIZE = (int) FP_REG.byteSize();
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dcall-argument-types.ll709 ; MESA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}}
710 ; HSA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}}
714 ; GCN-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:8
715 ; GCN-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12
717 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse…
718 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse…
724 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
725 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dcall-argument-types.ll709 ; MESA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}}
710 ; HSA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}}
714 ; GCN-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:8
715 ; GCN-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12
717 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse…
718 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse…
724 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
725 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dcall-argument-types.ll711 ; MESA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}}
712 ; HSA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x800{{$}}
716 ; GCN-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:8
717 ; GCN-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12
719 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse…
720 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offse…
726 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
727 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] off…
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/h8300/
H A Dh8300.h245 #define FRAME_POINTER_REGNUM FP_REG
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/h8300/
H A Dh8300.h245 #define FRAME_POINTER_REGNUM FP_REG
/dports/lang/gcc11/gcc-11.2.0/gcc/config/h8300/
H A Dh8300.h245 #define FRAME_POINTER_REGNUM FP_REG
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/h8300/
H A Dh8300.h245 #define FRAME_POINTER_REGNUM FP_REG
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/mcore/
H A Dmcore.h191 #define FP_REG 18 /* Fake frame pointer register. */ macro
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/ia64/
H A Dconstraints.md116 "Non-volatile memory for FP_REG loads/stores"
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/h8300/
H A Dh8300.h259 #define FRAME_POINTER_REGNUM FP_REG
/dports/lang/gcc9/gcc-9.4.0/gcc/config/mcore/
H A Dmcore.h191 #define FP_REG 18 /* Fake frame pointer register. */ macro
/dports/lang/gcc9/gcc-9.4.0/gcc/config/h8300/
H A Dh8300.h259 #define FRAME_POINTER_REGNUM FP_REG

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