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Searched refs:FP_ROUND (Results 226 – 250 of 551) sorted by relevance

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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp819 case ISD::FP_ROUND: in PreprocessISelDAG()
833 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1034 case ISD::FP_ROUND: in PreprocessISelDAG()
1065 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp819 case ISD::FP_ROUND: in PreprocessISelDAG()
833 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1034 case ISD::FP_ROUND: in PreprocessISelDAG()
1065 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp819 case ISD::FP_ROUND: in PreprocessISelDAG()
833 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1034 case ISD::FP_ROUND: in PreprocessISelDAG()
1065 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp251 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
253 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand); in SITargetLowering()
255 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand); in SITargetLowering()
257 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand); in SITargetLowering()
593 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in SITargetLowering()
4552 case ISD::FP_ROUND: in LowerOperation()
5128 DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
8304 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
8733 Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt, in performUCharToFloatCombine()
9300 case ISD::FP_ROUND: in fp16SrcZerosHighBits()
[all …]
H A DAMDGPUISelLowering.cpp2527 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2567 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3817 case ISD::FP_ROUND: { in performFNegCombine()
3822 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3831 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp199 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
201 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand); in SITargetLowering()
203 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand); in SITargetLowering()
205 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand); in SITargetLowering()
541 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in SITargetLowering()
4443 case ISD::FP_ROUND: in LowerOperation()
5019 DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
8225 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
8655 Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt, in performUCharToFloatCombine()
9222 case ISD::FP_ROUND: in fp16SrcZerosHighBits()
[all …]
H A DAMDGPUISelLowering.cpp2530 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2570 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3820 case ISD::FP_ROUND: { in performFNegCombine()
3825 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3834 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp199 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); in SITargetLowering()
201 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand); in SITargetLowering()
203 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand); in SITargetLowering()
205 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand); in SITargetLowering()
541 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in SITargetLowering()
4443 case ISD::FP_ROUND: in LowerOperation()
5019 DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
8225 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
8655 Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt, in performUCharToFloatCombine()
9222 case ISD::FP_ROUND: in fp16SrcZerosHighBits()
[all …]
H A DAMDGPUISelLowering.cpp2530 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2570 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3820 case ISD::FP_ROUND: { in performFNegCombine()
3825 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3834 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp249 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
250 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
402 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
408 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
668 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
2443 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2467 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
2924 case ISD::FP_ROUND: in LowerOperation()
4605 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
5272 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp246 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
247 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
399 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
405 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
653 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
2410 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2434 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
2896 case ISD::FP_ROUND: in LowerOperation()
4525 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
5192 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp246 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
247 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
397 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
403 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
651 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
2321 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2345 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
2827 case ISD::FP_ROUND: in LowerOperation()
4399 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
5021 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2514 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2554 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3827 case ISD::FP_ROUND: { in performFNegCombine()
3832 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3841 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2587 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2627 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3937 case ISD::FP_ROUND: { in performFNegCombine()
3942 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3951 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2587 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2627 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3937 case ISD::FP_ROUND: { in performFNegCombine()
3942 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3951 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2514 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2554 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3827 case ISD::FP_ROUND: { in performFNegCombine()
3832 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3841 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2587 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2627 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3937 case ISD::FP_ROUND: { in performFNegCombine()
3942 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3951 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2592 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2632 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3940 case ISD::FP_ROUND: { in performFNegCombine()
3945 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3954 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2587 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2627 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3937 case ISD::FP_ROUND: { in performFNegCombine()
3942 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3951 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2585 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2612 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3898 case ISD::FP_ROUND: { in performFNegCombine()
3903 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3912 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2587 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
2627 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
3937 case ISD::FP_ROUND: { in performFNegCombine()
3942 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3951 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/PowerPC/
H A DPPCISelLowering.cpp894 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
895 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
946 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
7637 Value = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
7787 FP = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
7860 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8122 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
12490 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, in combineElementTruncationToVectorTruncation()
12535 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
12913 FP = DAG.getNode(ISD::FP_ROUND, dl, in combineFPToIntToFP()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/PowerPC/
H A DPPCISelLowering.cpp857 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
858 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
908 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
7382 Value = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
7532 FP = DAG.getNode(ISD::FP_ROUND, dl, in LowerINT_TO_FP()
7605 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
7867 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
12031 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, in combineElementTruncationToVectorTruncation()
12071 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
12450 FP = DAG.getNode(ISD::FP_ROUND, dl, in combineFPToIntToFP()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/PowerPC/
H A DPPCISelLowering.cpp856 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
857 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
907 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
7254 Value = DAG.getNode(ISD::FP_ROUND, dl,
7404 FP = DAG.getNode(ISD::FP_ROUND, dl,
7477 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
7739 (V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
11826 SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl,
11866 if (FirstInput.getOpcode() == ISD::FP_ROUND &&
12244 FP = DAG.getNode(ISD::FP_ROUND, dl,
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1303 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
1395 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
1473 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, in getCastInstrCost()

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