| /dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/bfin/include/ |
| H A D | cdefblackfin.h | 138 #define pIMASK ((volatile unsigned short *)IMASK)
|
| H A D | def_LPBlackfin.h | 248 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/devel/gdb761/gdb-7.6.1/sim/testsuite/sim/bfin/ |
| H A D | se_cof.S | 106 LD32(p0, IMASK);
|
| H A D | se_kill_wbbr.S | 106 LD32(p0, IMASK);
|
| H A D | se_loop_disable.S | 106 LD32(p0, IMASK);
|
| H A D | se_rts_rti.S | 106 LD32(p0, IMASK);
|
| H A D | se_loop_ppm_int.S | 106 LD32(p0, IMASK);
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ |
| H A D | BF527_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| H A D | BF526_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ |
| H A D | BF526_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| H A D | BF527_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ |
| H A D | BF527_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| H A D | BF526_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ |
| H A D | BF526_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| H A D | BF527_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/devel/avr-gdb/gdb-7.3.1/sim/bfin/ |
| H A D | TODO | 27 - so long as SIC's IMASK allows it, bits set in ISR generate
|
| /dports/devel/gdb761/gdb-7.6.1/sim/bfin/ |
| H A D | TODO | 27 - so long as SIC's IMASK allows it, bits set in ISR generate
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ |
| H A D | BF527_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| H A D | BF526_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ |
| H A D | BF526_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| H A D | BF527_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ |
| H A D | BF526_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| H A D | BF527_def.h | 115 #define IMASK 0xFFE02104 /* Interrupt Mask Register */ macro
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-common/ |
| H A D | ADSP-EDN-core_cdef.h | 202 #define bfin_read_IMASK() bfin_read32(IMASK)
203 #define bfin_write_IMASK(val) bfin_write32(IMASK, val)
|
| /dports/graphics/dataplot/dataplot-2c1b27601a3b7523449de612613eadeead9a8f70/src/ |
| H A D | EDCOMM.INC | 70 CHARACTER*1 IMASK
259 1IPROSW,IPROMN,IMASK,IJUST,ISPACH,ISPACV,ITRANS,ICERAS,
|