| /dports/emulators/mame/mame-mame0226/3rdparty/bgfx/3rdparty/spirv-tools/source/opt/ |
| H A D | scalar_replacement_pass.h | 82 bool CheckType(const Instruction* typeInst) const;
99 bool CheckUses(const Instruction* inst) const;
111 void TransferAnnotations(const Instruction* source,
124 Pass::Status ReplaceVariable(Instruction* inst,
131 Instruction* GetStorageType(const Instruction* inst) const;
159 bool CreateReplacementVariables(Instruction* inst,
184 Instruction* newVar);
192 bool ReplaceWholeLoad(Instruction* load,
199 bool ReplaceWholeStore(Instruction* store,
206 bool ReplaceAccessChain(Instruction* chain,
[all …]
|
| /dports/lang/clover/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_nvc0.h | 70 void handleBREV(Instruction *);
73 void handleFTZ(Instruction *);
94 TexUse(Instruction *use, const Instruction *tex, bool after) in TexUse()
96 Instruction *insn;
108 inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
113 void addTexUse(std::list<TexUse>&, Instruction *, const Instruction *);
114 const Instruction *recurseDef(const Instruction *);
132 bool handleOUT(Instruction *);
133 bool handleDIV(Instruction *);
134 bool handleMOD(Instruction *);
[all …]
|
| /dports/emulators/qemu/qemu-6.2.0/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu42/qemu-4.2.1/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu60/qemu-6.0.0/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/www/firefox-legacy/firefox-52.8.0esr/js/src/jit/arm64/vixl/ |
| H A D | Disasm-vixl.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/libvixl/vixl/a64/ |
| H A D | disasm-a64.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/mozjs-45/extract/js/src/jit/arm64/vixl/ |
| H A D | Disasm-vixl.h | 51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr,
90 virtual void AppendCodeAddressToOutput(const Instruction* instr,
111 void Substitute(const Instruction* instr, const char* string);
117 const Instruction* instr, const char* format);
128 bool RdIsZROrSP(const Instruction* instr) const { in RdIsZROrSP()
132 bool RnIsZROrSP(const Instruction* instr) const { in RnIsZROrSP()
136 bool RmIsZROrSP(const Instruction* instr) const { in RmIsZROrSP()
140 bool RaIsZROrSP(const Instruction* instr) const { in RaIsZROrSP()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | TruncInstCombine.cpp | 54 case Instruction::ZExt: in getRelevantOperands()
55 case Instruction::SExt: in getRelevantOperands()
59 case Instruction::Add: in getRelevantOperands()
60 case Instruction::Sub: in getRelevantOperands()
61 case Instruction::Mul: in getRelevantOperands()
62 case Instruction::And: in getRelevantOperands()
63 case Instruction::Or: in getRelevantOperands()
64 case Instruction::Xor: in getRelevantOperands()
65 case Instruction::Shl: in getRelevantOperands()
66 case Instruction::LShr: in getRelevantOperands()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Transforms/Scalar/ |
| H A D | SpeculativeExecution.cpp | 217 case Instruction::Add:
218 case Instruction::Mul:
219 case Instruction::And:
220 case Instruction::Or:
222 case Instruction::Shl:
223 case Instruction::Sub:
224 case Instruction::LShr:
225 case Instruction::AShr:
226 case Instruction::Xor:
227 case Instruction::ZExt:
[all …]
|