| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/ |
| H A D | unal-altivec.ll | 37 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/ |
| H A D | unal-altivec.ll | 35 ; CHECK-DAG: lvx [[LD1:[0-9]+]], 0, [[C0:[0-9]+]]
38 ; CHECK-DAG: vperm [[VR1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/ |
| H A D | unal-altivec.ll | 37 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/ |
| H A D | unal-altivec.ll | 37 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/PowerPC/ |
| H A D | unal-altivec.ll | 37 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
| H A D | unal-altivec.ll | 37 ; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
|
| /dports/lang/go-devel/go-becaeea1199b875bc24800fa88f2f4fea119bf78/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| H A D | tables.go | 170 LD1 const
639 LD1: "LD1",
2337 …{0xbfffe000, 0x0d400000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offse…
2339 …{0xbfffe400, 0x0d404000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offse…
2341 …{0xbfffec00, 0x0d408000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, n…
2343 …{0xbffffc00, 0x0d408400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil…
2347 …{0xbfe0e000, 0x0dc00000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_…
2351 …{0xbfe0e400, 0x0dc04000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_…
2355 …{0xbfe0ec00, 0x0dc08000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, …
2357 …{0xbffffc00, 0x0ddf8400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedim…
[all …]
|
| /dports/lang/go-devel/go-dragonfly-amd64-bootstrap/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| H A D | tables.go | 170 LD1 const
639 LD1: "LD1",
2337 …{0xbfffe000, 0x0d400000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offse…
2339 …{0xbfffe400, 0x0d404000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offse…
2341 …{0xbfffec00, 0x0d408000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, n…
2343 …{0xbffffc00, 0x0d408400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil…
2347 …{0xbfe0e000, 0x0dc00000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_…
2351 …{0xbfe0e400, 0x0dc04000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_…
2355 …{0xbfe0ec00, 0x0dc08000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, …
2357 …{0xbffffc00, 0x0ddf8400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedim…
[all …]
|
| /dports/science/quantum-espresso/q-e-qe-6.7.0/atomic/Doc/ |
| H A D | Makefile | 30 -t "User's Guide for LD1" \
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
| H A D | load-bitcast-select.ll | 88 ; CHECK-NEXT: [[LD1:%.*]] = load float, float* [[LOADADDR1:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/Transforms/SLPVectorizer/X86/ |
| H A D | uitofp.ll | 27 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
36 ; AVX256-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
63 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
119 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to double
201 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i32 [[LD1]] to double
237 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i32 [[LD1]] to double
278 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i32 [[LD1]] to double
468 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i8 [[LD1]] to double
504 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i8 [[LD1]] to double
545 ; SSE-NEXT: [[CVT1:%.*]] = uitofp i8 [[LD1]] to double
[all …]
|