/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-rpi4/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/net/ |
H A D | mvpp2.c | 310 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3714 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3797 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3811 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 3982 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4216 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-riotboard/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-rpi2/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/u-boot-rpi3/u-boot-2021.07/drivers/net/ |
H A D | mvpp2.c | 319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro 3773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 3856 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 3870 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 4041 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 4275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Marvell/Drivers/Net/Pp2Dxe/ |
H A D | Mvpp2Lib.c | 2973 Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum); in Mvpp2DefaultsSet() 3057 Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum); in Mvpp2EgressEnable() 3072 Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum); in Mvpp2EgressDisable() 3363 Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum); in Mvpp2TxpMaxTxSizeSet() 3539 Mvpp2Write (Port->Priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, TxPortNum); in Mvpp2TxqHwInit()
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H A D | Mvpp2LibHw.h | 226 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
H A D | mvpp2.h | 383 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro
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H A D | mvpp2_main.c | 2245 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 2333 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 2347 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 2644 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 3111 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
H A D | mvpp2.h | 383 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro
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H A D | mvpp2_main.c | 2245 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 2333 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 2347 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 2644 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 3111 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
H A D | mvpp2.h | 383 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 macro
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H A D | mvpp2_main.c | 2245 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set() 2333 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable() 2347 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable() 2644 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set() 3111 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
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