| /dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/arm/mach-imx/mx6/ |
| H A D | clock.c | 244 return MXC_HCLK; in decode_pll()
263 return MXC_HCLK; in decode_pll()
317 freq = decode_pll(PLL_SYS, MXC_HCLK); in get_mcu_main_clk()
340 freq = MXC_HCLK; in get_periph_clk()
352 freq = decode_pll(PLL_BUS, MXC_HCLK); in get_periph_clk()
391 return MXC_HCLK; /* OSC 24Mhz */ in get_ipg_per_clk()
408 freq = MXC_HCLK; in get_uart_clk()
428 return MXC_HCLK / (cspi_podf + 1); in get_cspi_clk()
497 freq = MXC_HCLK; in get_mmdc_ch0_clk()
622 u32 hck = MXC_HCLK / 1000; in mxs_set_lcdclk()
[all …]
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 57 {MXC_HCLK, 24 * 16},
244 ret_val = MXC_HCLK; in get_lp_apm()
257 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
270 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
274 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
328 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
331 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
334 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
950 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 57 {MXC_HCLK, 24 * 16},
244 ret_val = MXC_HCLK; in get_lp_apm()
257 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
270 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
274 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
328 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
331 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
334 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
950 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 57 {MXC_HCLK, 24 * 16},
244 ret_val = MXC_HCLK; in get_lp_apm()
257 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
270 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
274 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
328 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
331 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
334 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
950 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 57 {MXC_HCLK, 24 * 16},
244 ret_val = MXC_HCLK; in get_lp_apm()
257 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
270 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
274 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
328 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
331 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
334 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
950 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 59 {MXC_HCLK, 24 * 16},
246 ret_val = MXC_HCLK; in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
[all …]
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