| /dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/xtensa/cpu/ |
| H A D | start.S | 29 #define PT_SAR 40 macro
424 s32i a2, a1, PT_SAR
481 l32i a2, a1, PT_SAR
|
| /dports/multimedia/libv4l/linux-5.13-rc2/arch/parisc/include/asm/ |
| H A D | assembly.h | 439 STREG %r1, PT_SAR (\regs)
441 SAVE_CR (%cr11, PT_SAR (\regs))
470 REST_CR (%cr11, PT_SAR (\regs))
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/parisc/include/asm/ |
| H A D | assembly.h | 439 STREG %r1, PT_SAR (\regs)
441 SAVE_CR (%cr11, PT_SAR (\regs))
470 REST_CR (%cr11, PT_SAR (\regs))
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/parisc/include/asm/ |
| H A D | assembly.h | 439 STREG %r1, PT_SAR (\regs)
441 SAVE_CR (%cr11, PT_SAR (\regs))
470 REST_CR (%cr11, PT_SAR (\regs))
|
| /dports/devel/avr-gdb/gdb-7.3.1/gdb/ |
| H A D | hppa-linux-offsets.h | 100 #define PT_SAR offsetof(struct pt_regs, sar) macro
|
| /dports/devel/gdb/gdb-11.1/gdb/ |
| H A D | hppa-linux-offsets.h | 103 #define PT_SAR offsetof(struct pt_regs, sar) macro
|
| /dports/devel/gdb761/gdb-7.6.1/gdb/ |
| H A D | hppa-linux-offsets.h | 100 #define PT_SAR offsetof(struct pt_regs, sar) macro
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/gdb/ |
| H A D | hppa-linux-nat.c | 84 PT_SAR,
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/gdb/ |
| H A D | hppa-linux-nat.c | 84 PT_SAR,
|
| /dports/multimedia/libv4l/linux-5.13-rc2/arch/parisc/kernel/ |
| H A D | ptrace.c | 175 addr == PT_SAR) { in arch_ptrace()
298 addr == PT_SAR+4) { in compat_arch_ptrace()
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/parisc/kernel/ |
| H A D | ptrace.c | 175 addr == PT_SAR) { in arch_ptrace()
298 addr == PT_SAR+4) { in compat_arch_ptrace()
|