| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/mips/lib/ |
| H A D | cache_init.S | 105 #define R_L2_LINE s6 macro
117 move R_L2_LINE, zero
150 ext R_L2_LINE, t1, \
152 beqz R_L2_LINE, l2_probe_done
154 sllv R_L2_LINE, t2, R_L2_LINE
158 mul R_L2_SIZE, R_L2_LINE, t2
193 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
194 beqz R_L2_LINE, l2_probe_done
196 sllv R_L2_LINE, t1, R_L2_LINE
201 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/mips/lib/ |
| H A D | cache_init.S | 120 #define R_L2_LINE s6 macro
132 move R_L2_LINE, zero
165 ext R_L2_LINE, t1, \
167 beqz R_L2_LINE, l2_probe_done
169 sllv R_L2_LINE, t2, R_L2_LINE
173 mul R_L2_SIZE, R_L2_LINE, t2
208 andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
209 beqz R_L2_LINE, l2_probe_done
211 sllv R_L2_LINE, t1, R_L2_LINE
216 mul R_L2_SIZE, R_L2_LINE, t1
[all …]
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