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Searched refs:SSCG_PLL_REF_DIVR1_MASK (Results 26 – 50 of 124) sorted by relevance

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/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dclock_imx8mq.h371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)

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