| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|