/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 59 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 60 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 61 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 59 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 60 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 61 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 59 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 60 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 61 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 59 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 60 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 61 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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H A D | HexagonGenPredicate.cpp | 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 324 WorkQ.push(PredReg); in isScalarPred() 326 while (!WorkQ.empty()) { in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 328 WorkQ.pop(); in isScalarPred() 356 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 59 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 60 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 61 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 59 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 60 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 61 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 59 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 60 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 61 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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H A D | HexagonGenPredicate.cpp | 322 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 323 WorkQ.push(PredReg); in isScalarPred() 325 while (!WorkQ.empty()) { in isScalarPred() 326 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 327 WorkQ.pop(); in isScalarPred() 355 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 60 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 61 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 62 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
H A D | RDFDeadCode.h | 60 void scanInstr(NodeAddr<InstrNode*> IA, SetQueue<NodeId> &WorkQ); 61 void processDef(NodeAddr<DefNode*> DA, SetQueue<NodeId> &WorkQ); 62 void processUse(NodeAddr<UseNode*> UA, SetQueue<NodeId> &WorkQ);
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/dports/devel/upp/upp/bazaar/WorkQueueTest2/ |
H A D | main.cpp | 11 workq <<= THISBACK(WorkQ); in WorkQueueTest() 24 void WorkQueueTest::WorkQ() in WorkQ() function in WorkQueueTest
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 324 WorkQ.push(PredReg); in isScalarPred() 326 while (!WorkQ.empty()) { in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 328 WorkQ.pop(); in isScalarPred() 356 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 324 WorkQ.push(PredReg); in isScalarPred() 326 while (!WorkQ.empty()) { in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 328 WorkQ.pop(); in isScalarPred() 356 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 324 WorkQ.push(PredReg); in isScalarPred() 326 while (!WorkQ.empty()) { in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 328 WorkQ.pop(); in isScalarPred() 356 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 324 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 325 WorkQ.push(PredReg); in isScalarPred() 327 while (!WorkQ.empty()) { in isScalarPred() 328 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 329 WorkQ.pop(); in isScalarPred() 357 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 324 WorkQ.push(PredReg); in isScalarPred() 326 while (!WorkQ.empty()) { in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 328 WorkQ.pop(); in isScalarPred() 356 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 323 std::queue<RegisterSubReg> WorkQ; in isScalarPred() local 324 WorkQ.push(PredReg); in isScalarPred() 326 while (!WorkQ.empty()) { in isScalarPred() 327 RegisterSubReg PR = WorkQ.front(); in isScalarPred() 328 WorkQ.pop(); in isScalarPred() 356 WorkQ.push(RegisterSubReg(MO.getReg())); in isScalarPred()
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