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Searched refs:XCHAL_HAVE_L32R (Results 226 – 250 of 427) sorted by relevance

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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/xtensa/variants/de212/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/xtensa/variants/csp/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/xtensa/variants/csp/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/xtensa/variants/de212/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/emulators/qemu42/qemu-4.2.1/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h66 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/xtensa/include/asm/arch-de212/
H A Dcore.h45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/arch/xtensa/variants/csp/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/arch/xtensa/variants/de212/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ macro

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