| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/clk/mediatek/ |
| H A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
32 .pcwbits = _pcwbits, \
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| H A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
30 .pcwbits = _pcwbits, \
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| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
32 .pcwbits = _pcwbits, \
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| H A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
30 .pcwbits = _pcwbits, \
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| H A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
32 .pcwbits = _pcwbits, \
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| H A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
30 .pcwbits = _pcwbits, \
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
32 .pcwbits = _pcwbits, \
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| H A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
30 .pcwbits = _pcwbits, \
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
32 .pcwbits = _pcwbits, \
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| H A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
30 .pcwbits = _pcwbits, \
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| H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
|
| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
30 .pcwbits = _pcwbits, \
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| H A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
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| H A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
32 .pcwbits = _pcwbits, \
|
| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
42 .pcwbits = _pcwbits, \
|