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Searched refs:cbcdr (Results 101 – 125 of 525) sorted by relevance

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/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c324 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
374 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
435 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
440 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
441 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
482 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
490 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1421 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1423 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1464 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/arm/mach-imx/mx6/
H A Dclock.c326 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
376 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
437 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk() local
442 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { in get_axi_clk()
443 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) in get_axi_clk()
484 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk() local
492 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { in get_mmdc_ch0_clk()
1434 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1436 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1477 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
[all …]

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