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Searched refs:expected0 (Results 51 – 75 of 352) sorted by relevance

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/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvzip.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvtrn.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 }; variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
11 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
15 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
18 VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; variable
19 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11, variable
23 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, 0x22, 0x22, variable
26 VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55, variable
[all …]
H A Dvuzp.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, variable
18 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, variable
20 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, variable
27 VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, variable
37 VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, variable
[all …]
H A Dvzip.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11, variable
9 VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2, variable
11 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
14 VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2, variable
16 VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55, variable
19 VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2, variable
[all …]
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
H A Dvdup-vmov.c9 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
12 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
13 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
14 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
18 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
19 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcc00, variable
35 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
45 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
227 CHECK_RESULTS_NAMED (TEST_MSG, expected0, ""); in exec_vdup_vmov()
[all …]
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
H A Dvdup-vmov.c9 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
12 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
13 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
14 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
18 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
19 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcc00, variable
35 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
45 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
227 CHECK_RESULTS_NAMED (TEST_MSG, expected0, ""); in exec_vdup_vmov()
[all …]
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
H A Dvdup-vmov.c9 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
12 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
13 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
14 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
18 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
19 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
23 VECT_VAR_DECL (expected0, hfloat, 16, 4) [] = { 0xcc00, 0xcc00, variable
35 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
45 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
227 CHECK_RESULTS_NAMED (TEST_MSG, expected0, ""); in exec_vdup_vmov()
[all …]
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvld1_dup.c7 VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
10 VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff0 }; variable
11 VECT_VAR_DECL(expected0,int,64,1) [] = { 0xfffffffffffffff0 }; variable
12 VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
16 VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; variable
17 VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
22 VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, variable
28 VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff0, variable
30 VECT_VAR_DECL(expected0,int,64,2) [] = { 0xfffffffffffffff0, variable
40 VECT_VAR_DECL(expected0,uint,64,2) [] = { 0xfffffffffffffff0, variable
[all …]

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