| /dports/lang/v8/v8-9.6.180.12/test/cctest/ |
| H A D | test-assembler-riscv64.cc | 495 UTEST_COMPARE_WITH_OP_F(feq_s, float, -3456.56, -3456.56, ==) in UTEST_CSRI()
1779 auto fn1 = [](MacroAssembler& assm) { __ feq_s(a0, fa0, fa1); }; in TEST() local
|
| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
| H A D | riscv-opc.h | 931 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
| H A D | riscv-opc.h | 985 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/devel/binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1033 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1033 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1033 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/devel/gdb/gdb-11.1/include/opcode/ |
| H A D | riscv-opc.h | 1033 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/disasm/ |
| H A D | disasm.cc | 917 DEFINE_FX2TYPE(feq_s); in disassembler_t()
|
| /dports/lang/v8/v8-9.6.180.12/src/codegen/riscv64/ |
| H A D | assembler-riscv64.h | 565 void feq_s(Register rd, FPURegister rs1, FPURegister rs2);
|
| H A D | assembler-riscv64.cc | 2013 void Assembler::feq_s(Register rd, FPURegister rs1, FPURegister rs2) { in feq_s() function in v8::internal::Assembler
|
| /dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
| H A D | encoding.h | 2200 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/lang/v8/v8-9.6.180.12/src/wasm/baseline/riscv64/ |
| H A D | liftoff-assembler-riscv64.h | 3165 feq_s(scratch, src, src); // rd <- !isNan(src) in emit_set_if_nan()
|
| /dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
| H A D | helper.h | 27 DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
|
| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
| H A D | helper.h | 27 DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
|
| /dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
| H A D | helper.h | 27 DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | encoding.h | 3231 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| /dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
| H A D | helper.h | 27 DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
|