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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/RISCV/
H A Dattribute-with-insts.s21 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
22 fmadd.d f10, f11, f12, f13, dyn
24 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
25 fmadd.s f10, f11, f12, f13, dyn
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/RISCV/
H A Dattribute-with-insts.s21 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
22 fmadd.d f10, f11, f12, f13, dyn
24 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
25 fmadd.s f10, f11, f12, f13, dyn
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/RISCV/
H A Dattribute-with-insts.s21 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
22 fmadd.d f10, f11, f12, f13, dyn
24 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
25 fmadd.s f10, f11, f12, f13, dyn
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/RISCV/
H A Dattribute-with-insts.s21 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
22 fmadd.d f10, f11, f12, f13, dyn
24 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
25 fmadd.s f10, f11, f12, f13, dyn
/dports/math/openblas/OpenBLAS-0.3.18/kernel/power/
H A Dzgemm_kernel_altivec_cell.S1168 fmadd f0, f8, f10, f0
1169 fmadd f2, f8, f11, f2
1170 fmadd f4, f8, f12, f4
1171 fmadd f6, f8, f13, f6
1173 fmadd f1, f9, f10, f1
1174 fmadd f3, f9, f11, f3
1175 fmadd f5, f9, f12, f5
1176 fmadd f7, f9, f13, f7
1186 fmadd f0, f8, f10, f0
1187 fmadd f2, f8, f11, f2
[all …]
H A Dzscal_hummer.S365 fmadd B2, ALPHA , A2, B2
375 fmadd B4, ALPHA , A4, B4
385 fmadd B6, ALPHA , A6, B6
395 fmadd B8, ALPHA , A8, B8
405 fmadd B2, ALPHA , A2, B2
417 fmadd B4, ALPHA , A4, B4
425 fmadd B6, ALPHA , A6, B6
429 fmadd B8, ALPHA , A8, B8
452 fmadd B2, ALPHA_I, A1, B2
454 fmadd B4, ALPHA_I, A3, B4
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/
H A Drecipest.ll19 ; CHECK-NEXT: fmadd
23 ; CHECK-NEXT: fmadd
42 ; CHECK-NOT: fmadd
44 ; CHECK-NOT: fmadd
79 ; CHECK-NEXT: fmadd
83 ; CHECK-NEXT: fmadd
177 ; CHECK: fmadd
179 ; CHECK-NEXT: fmadd
224 ; CHECK-NEXT: fmadd
228 ; CHECK-NEXT: fmadd
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/
H A Drecipest.ll20 ; CHECK-NEXT: fmadd
23 ; CHECK-NEXT: fmadd
41 ; CHECK-NOT: fmadd
43 ; CHECK-NOT: fmadd
79 ; CHECK-NEXT: fmadd
82 ; CHECK-NEXT: fmadd
176 ; CHECK: fmadd
178 ; CHECK-NEXT: fmadd
224 ; CHECK-NEXT: fmadd
227 ; CHECK-NEXT: fmadd
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/PowerPC/
H A Drecipest.ll20 ; CHECK-NEXT: fmadd
23 ; CHECK-NEXT: fmadd
41 ; CHECK-NOT: fmadd
43 ; CHECK-NOT: fmadd
79 ; CHECK-NEXT: fmadd
82 ; CHECK-NEXT: fmadd
176 ; CHECK: fmadd
178 ; CHECK-NEXT: fmadd
224 ; CHECK-NEXT: fmadd
227 ; CHECK-NEXT: fmadd
/dports/multimedia/opentoonz/opentoonz-1.5.0/thirdparty/openblas/xianyi-OpenBLAS-e6e87a2/kernel/power/
H A Dzscal_hummer.S365 fmadd B2, ALPHA , A2, B2
375 fmadd B4, ALPHA , A4, B4
385 fmadd B6, ALPHA , A6, B6
395 fmadd B8, ALPHA , A8, B8
405 fmadd B2, ALPHA , A2, B2
417 fmadd B4, ALPHA , A4, B4
425 fmadd B6, ALPHA , A6, B6
429 fmadd B8, ALPHA , A8, B8
452 fmadd B2, ALPHA_I, A1, B2
454 fmadd B4, ALPHA_I, A3, B4
[all …]
/dports/cad/meshlab/meshlab-Meshlab-2020.05/src/plugins_unsupported/external/GotoBLAS2/kernel/power/
H A Dzscal_hummer.S348 fmadd B2, ALPHA , A2, B2
358 fmadd B4, ALPHA , A4, B4
368 fmadd B6, ALPHA , A6, B6
378 fmadd B8, ALPHA , A8, B8
388 fmadd B2, ALPHA , A2, B2
400 fmadd B4, ALPHA , A4, B4
408 fmadd B6, ALPHA , A6, B6
412 fmadd B8, ALPHA , A8, B8
435 fmadd B2, ALPHA_I, A1, B2
437 fmadd B4, ALPHA_I, A3, B4
[all …]
/dports/math/gotoblas/GotoBLAS2/kernel/power/
H A Dzscal_hummer.S365 fmadd B2, ALPHA , A2, B2
375 fmadd B4, ALPHA , A4, B4
385 fmadd B6, ALPHA , A6, B6
395 fmadd B8, ALPHA , A8, B8
405 fmadd B2, ALPHA , A2, B2
417 fmadd B4, ALPHA , A4, B4
425 fmadd B6, ALPHA , A6, B6
429 fmadd B8, ALPHA , A8, B8
452 fmadd B2, ALPHA_I, A1, B2
454 fmadd B4, ALPHA_I, A3, B4
[all …]
/dports/multimedia/gstreamer1-plugins-rust/gst-plugins-rs-d0466b3eee114207f851b37cae0015c0e718f021/cargo-crates/rustfft-5.1.1/src/avx/
H A Davx64_butterflies.rs530 let twiddled110 = AvxVector::fmadd(mid110, self.twiddles[0], input0); in perform_fft_f64()
531 let twiddled38 = AvxVector::fmadd(mid110, self.twiddles[2], input0); in perform_fft_f64()
532 let twiddled29 = AvxVector::fmadd(mid110, self.twiddles[1], input0); in perform_fft_f64()
533 let twiddled47 = AvxVector::fmadd(mid110, self.twiddles[3], input0); in perform_fft_f64()
534 let twiddled56 = AvxVector::fmadd(mid110, self.twiddles[4], input0); in perform_fft_f64()
537 let twiddled38 = AvxVector::fmadd(mid29, self.twiddles[5], twiddled38); in perform_fft_f64()
538 let twiddled29 = AvxVector::fmadd(mid29, self.twiddles[3], twiddled29); in perform_fft_f64()
539 let twiddled47 = AvxVector::fmadd(mid29, self.twiddles[7], twiddled47); in perform_fft_f64()
540 let twiddled56 = AvxVector::fmadd(mid29, self.twiddles[9], twiddled56); in perform_fft_f64()
543 let twiddled38 = AvxVector::fmadd(mid38, self.twiddles[8], twiddled38); in perform_fft_f64()
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/
H A Dhalf-intrinsics.ll42 ; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
47 ; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
52 ; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
57 ; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
68 ; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
73 ; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
78 ; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
83 ; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/
H A Dhalf-intrinsics.ll42 ; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
47 ; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
52 ; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
57 ; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
68 ; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
73 ; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
78 ; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
83 ; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/msa/
H A D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d

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