| /dports/emulators/qemu/qemu-6.2.0/hw/net/ |
| H A D | e1000.c | 1180 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
1181 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
1183 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
1184 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
1185 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
1186 getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
1187 getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
1188 getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
1189 getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
1190 getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC),
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/hw/net/ |
| H A D | e1000.c | 1154 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
1155 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
1157 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
1158 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
1159 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
1160 getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
1161 getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
1162 getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
1163 getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
1164 getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC),
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/net/ |
| H A D | e1000.c | 1155 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
1156 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
1158 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
1159 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
1160 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
1161 getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
1162 getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
1163 getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
1164 getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
1165 getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC),
[all …]
|
| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/net/ |
| H A D | e1000.c | 1173 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
1174 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
1176 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
1177 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
1178 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
1179 getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
1180 getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
1181 getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
1182 getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
1183 getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC),
[all …]
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/net/ |
| H A D | e1000.c | 1155 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
1156 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
1158 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
1159 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
1160 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
1161 getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
1162 getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV),
1163 getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL),
1164 getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC),
1165 getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC),
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | regbankselect-amdgcn.s.getreg.mir | 6 name: getreg
11 ; CHECK-LABEL: name: getreg
12 …; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
13 %0:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg), 0
|
| /dports/editors/neovim/neovim-0.6.1/src/nvim/testdir/ |
| H A D | test_registers.vim | 151 call assert_equal('Xfile2', getreg('%'))
152 call assert_equal('Xfile1', getreg('#'))
155 call assert_equal('Two', getreg('.'))
156 call assert_equal('', getreg('_'))
161 call assert_equal('', getreg("\<C-F>"))
162 call assert_equal('', getreg("\<C-W>"))
163 call assert_equal('', getreg("\<C-L>"))
180 call assert_equal('Xfile_alt_1', getreg('#'))
182 call assert_equal('Xfile_alt_2', getreg('#'))
188 call assert_equal('regwrite', getreg('='))
[all …]
|
| /dports/editors/vim/vim-8.2.3745/src/testdir/ |
| H A D | test_registers.vim | 241 call assert_equal('Two', getreg('.'))
242 call assert_equal('', getreg('_'))
247 call assert_equal('', getreg("\<C-F>"))
253 call assert_equal('happy', getreg())
254 call assert_equal('happy', getreg(''))
320 call assert_equal('llhh', getreg('r'))
362 call assert_equal('text', getreg('*'))
370 call assert_equal('text', getreg('*'))
373 call assert_equal('food', getreg('*'))
380 call assert_equal('text', getreg('+'))
[all …]
|
| /dports/editors/neovim/neovim-0.6.1/test/functional/shada/ |
| H A D | merging_spec.lua | 251 eq('-', funcs.getreg('/'))
260 eq('?', funcs.getreg('/'))
269 eq('-', funcs.getreg('/'))
278 eq('?', funcs.getreg('/'))
286 eq('-', funcs.getreg('/'))
302 eq('-', funcs.getreg('/'))
318 eq('-', funcs.getreg('/'))
335 eq('-', funcs.getreg('/'))
344 eq('?', funcs.getreg('/'))
353 eq('-', funcs.getreg('/'))
[all …]
|
| /dports/editors/neovim/neovim-0.6.1/test/functional/ex_cmds/ |
| H A D | cmd_map_spec.lua | 345 eq({'some short l'}, funcs.getreg('a',1,1))
423 eq({'some short l'}, funcs.getreg('a',1,1))
428 eq({'some short l'}, funcs.getreg('b',1,1))
522 eq({'some short '}, funcs.getreg('"',1,1))
526 eq({'lines', 'of '}, funcs.getreg('"',1,1))
553 eq(funcs.getreg('b',1,1), {'me short lines', 'of t'})
624 eq(funcs.getreg('a',1,1), {'deed some short little lines', 'of stuff t'})
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/gdb/ |
| H A D | remote-hms.c | 116 hms_cmds.getreg.cmd = "r %s\r"; /* getreg.cmd (name) */ in init_hms_cmds()
117 hms_cmds.getreg.resp_delim = " ("; /* getreg.resp_delim */ in init_hms_cmds()
118 hms_cmds.getreg.term = ":"; /* getreg.term */ in init_hms_cmds()
119 hms_cmds.getreg.term_cmd = "\003"; /* getreg.term_cmd */ in init_hms_cmds()
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/gdb/ |
| H A D | remote-hms.c | 116 hms_cmds.getreg.cmd = "r %s\r"; /* getreg.cmd (name) */ in init_hms_cmds()
117 hms_cmds.getreg.resp_delim = " ("; /* getreg.resp_delim */ in init_hms_cmds()
118 hms_cmds.getreg.term = ":"; /* getreg.term */ in init_hms_cmds()
119 hms_cmds.getreg.term_cmd = "\003"; /* getreg.term_cmd */ in init_hms_cmds()
|