/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vmaxh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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H A D | vminh_f16_1.c | 18 float16_t input_1[] = { A, B, C, D }; variable 25 #define INPUT_1 input_1
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