/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/cpu/mcf532x/ |
H A D | interrupts.c | 15 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 18 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 19 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 28 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 30 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 31 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/cpu/mcf547x_8x/ |
H A D | interrupts.c | 15 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 18 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 19 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 29 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 31 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 32 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/cpu/mcf5227x/ |
H A D | interrupts.c | 18 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 21 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 22 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 31 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 33 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 34 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/cpu/mcf532x/ |
H A D | interrupts.c | 15 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 18 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 19 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 28 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 30 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 31 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/cpu/mcf5445x/ |
H A D | interrupts.c | 18 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 21 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 22 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 31 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 33 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 34 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/cpu/mcf547x_8x/ |
H A D | interrupts.c | 15 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 18 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 19 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 29 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 31 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 32 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/cpu/mcf5227x/ |
H A D | interrupts.c | 18 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 21 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 22 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 31 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 33 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 34 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/cpu/mcf5445x/ |
H A D | interrupts.c | 18 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 21 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 22 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 31 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 33 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 34 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/cpu/mcf547x_8x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 30 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 32 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 33 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/cpu/mcf532x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 29 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 31 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 32 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/cpu/mcf5445x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/cpu/mcf5227x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/m68k/cpu/mcf5227x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/m68k/cpu/mcf532x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 29 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 31 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 32 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/m68k/cpu/mcf5445x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/m68k/cpu/mcf547x_8x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 30 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 32 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 33 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/cpu/mcf532x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 29 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 31 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 32 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/cpu/mcf5227x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/cpu/mcf547x_8x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 30 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 32 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 33 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/cpu/mcf5445x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/m68k/cpu/mcf5445x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/m68k/cpu/mcf5227x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/m68k/cpu/mcf532x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 29 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 31 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 32 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/m68k/cpu/mcf547x_8x/ |
H A D | interrupts.c | 16 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 19 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 20 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 30 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 32 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 33 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/m68k/cpu/mcf5227x/ |
H A D | interrupts.c | 19 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in interrupt_init() local 22 setbits_be32(&intp->imrh0, 0xffffffff); in interrupt_init() 23 setbits_be32(&intp->imrl0, 0xffffffff); in interrupt_init() 32 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); in dtimer_intr_setup() local 34 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); in dtimer_intr_setup() 35 clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); in dtimer_intr_setup()
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