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Searched refs:mr1 (Results 201 – 225 of 2288) sorted by relevance

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/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-tools/u-boot-2020.07/board/imgtec/ci20/
H A Dci20.c291 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
293 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
335 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
337 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/imgtec/ci20/
H A Dci20.c288 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
290 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
332 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
334 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-rpi/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/board/imgtec/ci20/
H A Dci20.c292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),

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