| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 142 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
152 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
155 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
158 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
161 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
165 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
168 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-rock64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
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| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 147 unsigned short pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get() local
160 pri_and_ext_bus_width = BUS_MASK_16BIT; in mv_ddr_bus_bit_mask_get()
163 pri_and_ext_bus_width = BUS_MASK_32BIT; in mv_ddr_bus_bit_mask_get()
166 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK; in mv_ddr_bus_bit_mask_get()
169 pri_and_ext_bus_width = 0x0; in mv_ddr_bus_bit_mask_get()
173 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1); in mv_ddr_bus_bit_mask_get()
176 return pri_and_ext_bus_width; in mv_ddr_bus_bit_mask_get()
|