Home
last modified time | relevance | path

Searched refs:rl_val (Results 76 – 100 of 188) sorted by relevance

12345678

/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1690 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1742 rl_val = 0; in mv_ddr_rl_dqs_burst()
1759 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1764 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1940 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1943 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1690 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM];
1742 rl_val = 0;
1759 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) |
1764 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val);
1940 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) |
1943 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val);
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()

12345678