Searched refs:shiftReg (Results 26 – 27 of 27) sorted by relevance
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| /dports/lang/spidermonkey78/firefox-78.9.0/js/src/jit/arm/ |
| H A D | Assembler-arm.h | 701 explicit Op2Reg(Register rm, ShiftType type, datastore::RRS shiftReg) in Op2Reg() argument
702 : Operand2(datastore::Reg(rm.code(), type, 1, shiftReg.encode())) {} in Op2Reg()
770 explicit DtrOffReg(Register rn, ShiftType type, datastore::RRS shiftReg,
772 : DtrOff(datastore::Reg(rn.code(), type, 1, shiftReg.encode()), iu) {}
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| /dports/lang/polyml/polyml-5.8.2/mlsource/MLCompiler/CodeTree/X86Code/ |
| H A D | X86ICodeToX86Code.ML | 1298 … shiftAmount=RegisterArgument(PReg shiftReg), opSize, ...}, ...}, code) =
1301 val realShiftReg = getAllocatedReg shiftReg
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