Home
last modified time | relevance | path

Searched refs:sim_warn (Results 26 – 28 of 28) sorted by relevance

12

/dports/emulators/dps8m/dps8m-572f79bb4f0f84a8b16c3892c894c2b9ed64b458/src/dps8/
H A Ddps8_append.c1384 sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode); in do_append_cycle()
1412 sim_warn ("do_append_cycle(B) boolA %d != boolB %d cycle %s insflag %d\n", in do_append_cycle()
1547 sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", in do_append_cycle()
1920 sim_warn("do_append_cycle: RMW nWords %d !=1\n", nWords); in do_append_cycle()
H A Ddps8_ins.c507 sim_warn("%s: scu rewrite %d: %s\n", __func__, i, rewrite_table[i].name); in scu2words()
2159 sim_warn("executeInstruction: operand_size!= 1\n"); in executeInstruction()
2161sim_warn("executeInstruction: write addr changed %o %d\n", cpu.iefpFinalAddress, cpu.rmw_address); in executeInstruction()
7138 sim_warn ("rccl on CPU %u port %d has no SCU; faulting\n", in doInstruction()
7493 sim_warn ("LCPR set csh_reg\n"); in doInstruction()
7601 sim_warn ("LCPR set SDPAP\n"); in doInstruction()
7606 sim_warn ("LCPR set SEPAR\n"); in doInstruction()
8243 sim_warn ("CAMP ignores enable/disable %06o\n", cpu.TPR.CA); in doInstruction()
8295 sim_warn ("CAMS ignores enable/disable %06o\n", cpu.TPR.CA); in doInstruction()
8325 sim_warn ("rmcm to non-existent controller on " in doInstruction()
[all …]
H A Ddps8_iefp.c379 sim_warn ("ReadPage not on boundary %06o\n", address); in ReadPage()
892 sim_warn ("WritePage not on boundary %06o\n", address); in WritePage()

12