/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
H A D | vst3q_lane_u64_indices_1.c | 8 f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v) in f_vst3q_lane_u64()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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H A D | arm-vst1.ll | 29 ; %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 55 %struct.uint64x2x3_t = type { [3 x <2 x i64>] } 308 define void @test_vst1q_u64_x3(i64* %a, %struct.uint64x2x3_t %b) nounwind { 310 %b0 = extractvalue %struct.uint64x2x3_t %b, 0, 0 311 %b1 = extractvalue %struct.uint64x2x3_t %b, 0, 1 312 %b2 = extractvalue %struct.uint64x2x3_t %b, 0, 2
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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H A D | arm-vst1.ll | 29 ; %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 55 %struct.uint64x2x3_t = type { [3 x <2 x i64>] } 308 define void @test_vst1q_u64_x3(i64* %a, %struct.uint64x2x3_t %b) nounwind { 310 %b0 = extractvalue %struct.uint64x2x3_t %b, 0, 0 311 %b1 = extractvalue %struct.uint64x2x3_t %b, 0, 1 312 %b2 = extractvalue %struct.uint64x2x3_t %b, 0, 2
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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H A D | arm-vst1.ll | 29 ; %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 55 %struct.uint64x2x3_t = type { [3 x <2 x i64>] } 308 define void @test_vst1q_u64_x3(i64* %a, %struct.uint64x2x3_t %b) nounwind { 310 %b0 = extractvalue %struct.uint64x2x3_t %b, 0, 0 311 %b1 = extractvalue %struct.uint64x2x3_t %b, 0, 1 312 %b2 = extractvalue %struct.uint64x2x3_t %b, 0, 2
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/ARM/ |
H A D | arm-vld1.ll | 29 %struct.uint64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> } 61 declare %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64*) nounwind readonly 208 define %struct.uint64x2x3_t @test_vld1q_u64_x3(i64* %a) nounwind { 209 %tmp = tail call %struct.uint64x2x3_t @llvm.arm.neon.vld1x3.v2i64.p0i64(i64* %a) 210 ret %struct.uint64x2x3_t %tmp
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/dports/math/py-numpy/numpy-1.20.3/numpy/core/src/common/simd/neon/ |
H A D | neon.h | 51 typedef uint64x2x3_t npyv_u64x3;
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