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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll229 ; CHECK-NEXT: uminv b0, p0, z0.b
232 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
240 ; CHECK-NEXT: uminv h0, p0, z0.h
243 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
251 ; CHECK-NEXT: uminv s0, p0, z0.s
254 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
262 ; CHECK-NEXT: uminv d0, p0, z0.d
265 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
422 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
423 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Dsve-implicit-zero-filling.ll148 ; CHECK: uminv d0, p0, z0.d
150 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
160 ; CHECK: uminv d{{[0-9]+}}, p0, z0.d
163 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
172 ; CHECK: uminv d0, p0, z0.d
175 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
234 declare i8 @llvm.aarch64.sve.uminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
235 declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll233 ; CHECK-NEXT: uminv b0, p0, z0.b
236 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
244 ; CHECK-NEXT: uminv h0, p0, z0.h
247 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
255 ; CHECK-NEXT: uminv s0, p0, z0.s
258 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
266 ; CHECK-NEXT: uminv d0, p0, z0.d
269 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
426 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
427 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll211 ; CHECK: uminv b[[REDUCE:[0-9]+]], p0, z0.b
214 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
221 ; CHECK: uminv h[[REDUCE:[0-9]+]], p0, z0.h
224 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
231 ; CHECK: uminv s[[REDUCE:[0-9]+]], p0, z0.s
234 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
241 ; CHECK: uminv d[[REDUCE:[0-9]+]], p0, z0.d
244 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
389 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
390 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll229 ; CHECK-NEXT: uminv b0, p0, z0.b
232 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
240 ; CHECK-NEXT: uminv h0, p0, z0.h
243 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
251 ; CHECK-NEXT: uminv s0, p0, z0.s
254 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
262 ; CHECK-NEXT: uminv d0, p0, z0.d
265 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
422 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
423 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
H A Dsve-implicit-zero-filling.ll165 ; CHECK-NEXT: uminv d0, p0, z0.d
167 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
179 ; CHECK-NEXT: uminv d0, p0, z0.d
188 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
199 ; CHECK-NEXT: uminv d0, p0, z0.d
201 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
264 declare i8 @llvm.aarch64.sve.uminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
265 declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll229 ; CHECK-NEXT: uminv b0, p0, z0.b
232 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
240 ; CHECK-NEXT: uminv h0, p0, z0.h
243 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
251 ; CHECK-NEXT: uminv s0, p0, z0.s
254 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
262 ; CHECK-NEXT: uminv d0, p0, z0.d
265 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
422 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
423 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Dsve-implicit-zero-filling.ll148 ; CHECK: uminv d0, p0, z0.d
150 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
160 ; CHECK: uminv d{{[0-9]+}}, p0, z0.d
163 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
172 ; CHECK: uminv d0, p0, z0.d
175 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
234 declare i8 @llvm.aarch64.sve.uminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
235 declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll233 ; CHECK-NEXT: uminv b0, p0, z0.b
236 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
244 ; CHECK-NEXT: uminv h0, p0, z0.h
247 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
255 ; CHECK-NEXT: uminv s0, p0, z0.s
258 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
266 ; CHECK-NEXT: uminv d0, p0, z0.d
269 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
426 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
427 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll207 ; CHECK: uminv b[[REDUCE:[0-9]+]], p0, z0.b
210 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
217 ; CHECK: uminv h[[REDUCE:[0-9]+]], p0, z0.h
220 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
227 ; CHECK: uminv s[[REDUCE:[0-9]+]], p0, z0.s
230 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
237 ; CHECK: uminv d[[REDUCE:[0-9]+]], p0, z0.d
240 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
385 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
386 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-int-reduce-pred.ll229 ; CHECK-NEXT: uminv b0, p0, z0.b
232 %out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
240 ; CHECK-NEXT: uminv h0, p0, z0.h
243 %out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
251 ; CHECK-NEXT: uminv s0, p0, z0.s
254 %out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
262 ; CHECK-NEXT: uminv d0, p0, z0.d
265 %out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
422 declare i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
423 declare i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
[all …]
H A Dsve-implicit-zero-filling.ll148 ; CHECK: uminv d0, p0, z0.d
150 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
160 ; CHECK: uminv d{{[0-9]+}}, p0, z0.d
163 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
172 ; CHECK: uminv d0, p0, z0.d
175 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
234 declare i8 @llvm.aarch64.sve.uminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
235 declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dsve-implicit-zero-filling.ll148 ; CHECK: uminv d0, p0, z0.d
150 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
160 ; CHECK: uminv d{{[0-9]+}}, p0, z0.d
163 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
172 ; CHECK: uminv d0, p0, z0.d
175 %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
234 declare i8 @llvm.aarch64.sve.uminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
235 declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/
H A Daarch64-minmaxv.ll95 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
103 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
111 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
163 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
176 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]

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