/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | extractelement.i16.ll | 33 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0 46 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0 59 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0 72 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v2 78 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0 85 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v2 91 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0 98 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 1, v2 104 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 115 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v0 [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | extractelement.i16.ll | 33 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, s0, v0 46 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, s0, v0 59 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, s0, v0 72 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v2 78 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, v1, v0 85 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v2 91 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, v1, v0 98 ; GFX7-NEXT: v_lshrrev_b32_e32 v3, 1, v2 104 ; GFX7-NEXT: v_lshrrev_b32_e32 v0, v1, v0 115 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v0 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | idot8s.ll | 421 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 4, v3 423 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 28, v3 424 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 20, v3 426 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 4, v2 428 ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 12, v3 429 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v3 433 ; GFX8-NEXT: v_lshrrev_b32_e32 v14, 8, v2 494 ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 4, v1 496 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 4, v2 499 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 28, v1 [all …]
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H A D | srem-seteq-illegal-types.ll | 28 ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1 72 ; CHECK-NEXT: v_lshrrev_b32_e32 v6, 31, v5 73 ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5 74 ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 31, v4 75 ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 1, v4 76 ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v3 77 ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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H A D | fmax_legacy.f16.ll | 66 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 85 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 163 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 261 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 264 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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H A D | fmin_legacy.f16.ll | 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 68 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 87 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 165 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 263 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 266 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | idot8s.ll | 421 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 4, v3 423 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 28, v3 424 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 20, v3 426 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 4, v2 428 ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 12, v3 429 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v3 433 ; GFX8-NEXT: v_lshrrev_b32_e32 v14, 8, v2 494 ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 4, v1 496 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 4, v2 499 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 28, v1 [all …]
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H A D | srem-seteq-illegal-types.ll | 28 ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1 72 ; CHECK-NEXT: v_lshrrev_b32_e32 v6, 31, v5 73 ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5 74 ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 31, v4 75 ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 1, v4 76 ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v3 77 ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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H A D | fmin_legacy.f16.ll | 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 68 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 87 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 165 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 263 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 266 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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H A D | fmax_legacy.f16.ll | 66 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 85 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 163 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 261 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 264 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | idot8s.ll | 421 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 4, v3 423 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 28, v3 424 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 20, v3 425 ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 12, v3 426 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v3 428 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 4, v2 433 ; GFX8-NEXT: v_lshrrev_b32_e32 v14, 8, v2 494 ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 4, v1 496 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 4, v2 499 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 28, v1 [all …]
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H A D | srem-seteq-illegal-types.ll | 28 ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1 72 ; CHECK-NEXT: v_lshrrev_b32_e32 v6, 31, v5 73 ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5 74 ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 31, v4 75 ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 1, v4 76 ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v3 77 ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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H A D | fmin_legacy.f16.ll | 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 68 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 87 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 165 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 263 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 264 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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H A D | fmax_legacy.f16.ll | 66 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 85 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 163 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 261 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 263 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 264 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | idot8s.ll | 421 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 4, v3 423 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 28, v3 424 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 20, v3 426 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 4, v2 428 ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 12, v3 429 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v3 433 ; GFX8-NEXT: v_lshrrev_b32_e32 v14, 8, v2 494 ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 4, v1 496 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 4, v2 499 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 28, v1 [all …]
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H A D | srem-seteq-illegal-types.ll | 28 ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1 72 ; CHECK-NEXT: v_lshrrev_b32_e32 v6, 31, v5 73 ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5 74 ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 31, v4 75 ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 1, v4 76 ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v3 77 ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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H A D | fmax_legacy.f16.ll | 66 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 85 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 163 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 261 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 264 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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H A D | fmin_legacy.f16.ll | 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 68 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 87 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 165 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 263 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 266 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | idot8s.ll | 421 ; GFX8-NEXT: v_lshrrev_b32_e32 v10, 4, v3 423 ; GFX8-NEXT: v_lshrrev_b32_e32 v6, 28, v3 424 ; GFX8-NEXT: v_lshrrev_b32_e32 v7, 20, v3 426 ; GFX8-NEXT: v_lshrrev_b32_e32 v15, 4, v2 428 ; GFX8-NEXT: v_lshrrev_b32_e32 v8, 12, v3 429 ; GFX8-NEXT: v_lshrrev_b32_e32 v9, 8, v3 433 ; GFX8-NEXT: v_lshrrev_b32_e32 v14, 8, v2 494 ; GFX9-NEXT: v_lshrrev_b32_e32 v9, 4, v1 496 ; GFX9-NEXT: v_lshrrev_b32_e32 v14, 4, v2 499 ; GFX9-NEXT: v_lshrrev_b32_e32 v5, 28, v1 [all …]
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H A D | srem-seteq-illegal-types.ll | 28 ; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1 72 ; CHECK-NEXT: v_lshrrev_b32_e32 v6, 31, v5 73 ; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5 74 ; CHECK-NEXT: v_lshrrev_b32_e32 v7, 31, v4 75 ; CHECK-NEXT: v_lshrrev_b32_e32 v4, 1, v4 76 ; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v3 77 ; CHECK-NEXT: v_lshrrev_b32_e32 v3, 1, v3
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H A D | fmax_legacy.f16.ll | 66 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 85 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 163 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 261 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 264 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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H A D | fmin_legacy.f16.ll | 67 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 68 ; GFX9-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 86 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 87 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 164 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 165 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 262 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v6, 16, v3 263 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v7, 16, v1 265 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 16, v2 266 ; VI-SAFE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | lshr.ll | 13 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 36 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 7, v0 102 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 113 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 7, v0 145 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 155 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 202 ; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0 213 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0 214 ; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1 224 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | lshr.ll | 13 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0 36 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 7, v0 102 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 113 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 7, v0 145 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 155 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 202 ; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0 213 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0 214 ; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1 224 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0 [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/ |
H A D | llvm.fma.f16.ll | 108 ; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 109 ; SI: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]] 110 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 124 ; VI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 125 ; VI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 126 ; VI: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]] 159 ; GCN-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 160 ; GCN-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]] 202 ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 244 ; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] [all …]
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