/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/ppc/translate/ |
H A D | vmx-impl.inc.c | 377 GEN_VXFORM(vminuh, 1, 9);
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/dports/textproc/highlight/highlight-4.1/langDefs/ |
H A D | s.lang | 43 "vminuh", "vminuw", "vmladduhm", "vmrghb", "vmrghh", "vmrghw", "vmrglb",
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Hexagon/ |
H A D | intrinsics-v60-alu.ll | 423 %0 = tail call <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32> %a, <16 x i32> %b) 967 declare <16 x i32> @llvm.hexagon.V6.vminuh(<16 x i32>, <16 x i32>) #0
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/dports/lang/gcc9-aux/bootstrap/lib/gcc/x86_64-aux-dragonfly5.5/9.1.0/adalib/ |
H A D | g-allein.ali | 439 169V13*vminuh{50R9} 419i<c,__builtin_altivec_vminuh>31
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/dports/lang/gcc6-aux/bootstrap/lib/gcc/x86_64-aux-dragonfly4.1/5.1.0/adalib/ |
H A D | g-allein.ali | 437 169V13*vminuh{50R9} 419i<c,__builtin_altivec_vminuh>31
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/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/include/llvm/IR/ |
H A D | IntrinsicsPowerPC.td | 429 def int_ppc_altivec_vminuh : PowerPC_Vec_HHH_Intrinsic<"vminuh">;
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/dports/emulators/qemu-utils/qemu-4.2.1/target/ppc/translate/ |
H A D | vmx-impl.inc.c | 427 GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
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/dports/emulators/qemu/qemu-6.2.0/capstone/arch/PowerPC/ |
H A D | PPCMappingInsnName.inc | 1306 "vminuh", // PPC_INS_VMINUH,
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/dports/emulators/qemu60/qemu-6.0.0/capstone/arch/PowerPC/ |
H A D | PPCMappingInsnName.inc | 1306 "vminuh", // PPC_INS_VMINUH,
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/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/include/llvm/IR/ |
H A D | IntrinsicsPowerPC.td | 429 def int_ppc_altivec_vminuh : PowerPC_Vec_HHH_Intrinsic<"vminuh">;
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/ppc/translate/ |
H A D | vmx-impl.inc.c | 427 GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
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