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Searched refs:vspltisw (Results 76 – 100 of 773) sorted by relevance

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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/PowerPC/
H A Dvaddsplat.ll20 ; CHECK: vspltisw [[REG1:[0-9]+]], 9
31 ; CHECK: vspltisw [[REG1:[0-9]+]], -14
86 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
87 ; CHECK: vspltisw [[REG1:[0-9]+]], 11
98 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
99 ; CHECK: vspltisw [[REG1:[0-9]+]], -11
H A Dsignbit-shift.ll198 ; CHECK-NEXT: vspltisw 3, -16
199 ; CHECK-NEXT: vspltisw 4, 15
228 ; CHECK-NEXT: vspltisw 3, -16
229 ; CHECK-NEXT: vspltisw 4, 15
257 ; CHECK-NEXT: vspltisw 4, -16
258 ; CHECK-NEXT: vspltisw 5, 15
282 ; CHECK-NEXT: vspltisw 3, -16
283 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dvaddsplat.ll20 ; CHECK: vspltisw [[REG1:[0-9]+]], 9
31 ; CHECK: vspltisw [[REG1:[0-9]+]], -14
86 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
87 ; CHECK: vspltisw [[REG1:[0-9]+]], 11
98 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
99 ; CHECK: vspltisw [[REG1:[0-9]+]], -11
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/security/nettle/nettle-3.7.3/powerpc64/p7/
H A Dchacha-core-internal.asm102 vspltisw ROT16, -16 C -16 instead of 16 actually works!
103 vspltisw ROT12, 12
104 vspltisw ROT8, 8
105 vspltisw ROT7, 7
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll191 ; CHECK-NEXT: vspltisw 3, -16
192 ; CHECK-NEXT: vspltisw 4, 15
221 ; CHECK-NEXT: vspltisw 3, -16
222 ; CHECK-NEXT: vspltisw 4, 15
250 ; CHECK-NEXT: vspltisw 4, -16
251 ; CHECK-NEXT: vspltisw 5, 15
275 ; CHECK-NEXT: vspltisw 3, -16
276 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll197 ; CHECK-NEXT: vspltisw 3, -16
198 ; CHECK-NEXT: vspltisw 4, 15
227 ; CHECK-NEXT: vspltisw 3, -16
228 ; CHECK-NEXT: vspltisw 4, 15
256 ; CHECK-NEXT: vspltisw 4, -16
257 ; CHECK-NEXT: vspltisw 5, 15
281 ; CHECK-NEXT: vspltisw 3, -16
282 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll197 ; CHECK-NEXT: vspltisw 3, -16
198 ; CHECK-NEXT: vspltisw 4, 15
227 ; CHECK-NEXT: vspltisw 3, -16
228 ; CHECK-NEXT: vspltisw 4, 15
256 ; CHECK-NEXT: vspltisw 4, -16
257 ; CHECK-NEXT: vspltisw 5, 15
281 ; CHECK-NEXT: vspltisw 3, -16
282 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll197 ; CHECK-NEXT: vspltisw 3, -16
198 ; CHECK-NEXT: vspltisw 4, 15
227 ; CHECK-NEXT: vspltisw 3, -16
228 ; CHECK-NEXT: vspltisw 4, 15
256 ; CHECK-NEXT: vspltisw 4, -16
257 ; CHECK-NEXT: vspltisw 5, 15
281 ; CHECK-NEXT: vspltisw 3, -16
282 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll197 ; CHECK-NEXT: vspltisw 3, -16
198 ; CHECK-NEXT: vspltisw 4, 15
227 ; CHECK-NEXT: vspltisw 3, -16
228 ; CHECK-NEXT: vspltisw 4, 15
256 ; CHECK-NEXT: vspltisw 4, -16
257 ; CHECK-NEXT: vspltisw 5, 15
281 ; CHECK-NEXT: vspltisw 3, -16
282 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll198 ; CHECK-NEXT: vspltisw 3, -16
199 ; CHECK-NEXT: vspltisw 4, 15
228 ; CHECK-NEXT: vspltisw 3, -16
229 ; CHECK-NEXT: vspltisw 4, 15
257 ; CHECK-NEXT: vspltisw 4, -16
258 ; CHECK-NEXT: vspltisw 5, 15
282 ; CHECK-NEXT: vspltisw 3, -16
283 ; CHECK-NEXT: vspltisw 4, 15
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/
H A Dsignbit-shift.ll197 ; CHECK-NEXT: vspltisw 3, -16
198 ; CHECK-NEXT: vspltisw 4, 15
227 ; CHECK-NEXT: vspltisw 3, -16
228 ; CHECK-NEXT: vspltisw 4, 15
256 ; CHECK-NEXT: vspltisw 4, -16
257 ; CHECK-NEXT: vspltisw 5, 15
281 ; CHECK-NEXT: vspltisw 3, -16
282 ; CHECK-NEXT: vspltisw 4, 15
H A Dfunnel-shift-rot.ll93 ; CHECK-NEXT: vspltisw 3, -16
94 ; CHECK-NEXT: vspltisw 4, 13
95 ; CHECK-NEXT: vspltisw 5, 3
184 ; CHECK-NEXT: vspltisw 3, -16
185 ; CHECK-NEXT: vspltisw 4, 13
186 ; CHECK-NEXT: vspltisw 5, 3
/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/linux-ppc64le/asm/crypto/chacha/
H A Dchacha-ppc.s432 vspltisw 26,-1
487 vspltisw 27,12
488 vspltisw 28,7
1024 vspltisw 27,-16
1025 vspltisw 28,12
1026 vspltisw 29,8
1027 vspltisw 30,7
1161 vspltisw 27,4
/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/linux-ppc64le/asm_avx2/crypto/chacha/
H A Dchacha-ppc.s432 vspltisw 26,-1
487 vspltisw 27,12
488 vspltisw 28,7
1024 vspltisw 27,-16
1025 vspltisw 28,12
1026 vspltisw 29,8
1027 vspltisw 30,7
1161 vspltisw 27,4
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp477 struct vspltisw : public Operator { struct
478 vspltisw(const char *N, unsigned Opc) in vspltisw() argument
482 vspltisw<0> the_vspltisw0("vspltisw0", OP_VSPLTISW0);
483 vspltisw<1> the_vspltisw1("vspltisw1", OP_VSPLTISW1);
484 vspltisw<2> the_vspltisw2("vspltisw2", OP_VSPLTISW2);
485 vspltisw<3> the_vspltisw3("vspltisw3", OP_VSPLTISW3);
/dports/devel/llvm11/llvm-11.0.1.src/utils/PerfectShuffle/
H A DPerfectShuffle.cpp477 struct vspltisw : public Operator { struct
478 vspltisw(const char *N, unsigned Opc) in vspltisw() function
482 vspltisw<0> the_vspltisw0("vspltisw0", OP_VSPLTISW0);
483 vspltisw<1> the_vspltisw1("vspltisw1", OP_VSPLTISW1);
484 vspltisw<2> the_vspltisw2("vspltisw2", OP_VSPLTISW2);
485 vspltisw<3> the_vspltisw3("vspltisw3", OP_VSPLTISW3);
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp477 struct vspltisw : public Operator { struct
478 vspltisw(const char *N, unsigned Opc) in vspltisw() function
482 vspltisw<0> the_vspltisw0("vspltisw0", OP_VSPLTISW0);
483 vspltisw<1> the_vspltisw1("vspltisw1", OP_VSPLTISW1);
484 vspltisw<2> the_vspltisw2("vspltisw2", OP_VSPLTISW2);
485 vspltisw<3> the_vspltisw3("vspltisw3", OP_VSPLTISW3);
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp477 struct vspltisw : public Operator { struct
478 vspltisw(const char *N, unsigned Opc) in vspltisw() function
482 vspltisw<0> the_vspltisw0("vspltisw0", OP_VSPLTISW0);
483 vspltisw<1> the_vspltisw1("vspltisw1", OP_VSPLTISW1);
484 vspltisw<2> the_vspltisw2("vspltisw2", OP_VSPLTISW2);
485 vspltisw<3> the_vspltisw3("vspltisw3", OP_VSPLTISW3);

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