Searched refs:wrreq (Results 26 – 31 of 31) sorted by relevance
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| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_altera_lpm.v | 5425 wrreq,
5445 input wrreq; port
5729 wrreq && !full_flag;
6062 wrreq,
6089 input wrreq; port
6314 .wreq (wrreq),
6323 .wreq(wrreq),
6465 assign w_wren = (i_overflow_checking == "OFF") ? wrreq : wrreq && !w_wrfull;
6499 wrreq,
6530 input wrreq; port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | rx_buffer.v | 91 .wrreq (~rx_full & (phase != 0)),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_2k.v | 3024 wrreq,
3036 input wrreq; port
3209 valid_wrreq = wrreq,
3221 wrreq,
3233 input wrreq; port
3260 .wrreq (wrreq),
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| H A D | fifo_4k.v | 3176 wrreq,
3188 input wrreq; port
3361 valid_wrreq = wrreq,
3373 wrreq,
3385 input wrreq; port
3412 .wrreq (wrreq),
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug17309/ |
| H A D | polyamplib.vhdl | 63 wrreq : in std_logic; port in polyamplib.fifo_memory
78 wrreq : in std_logic; port in polyamplib.fifo_ft_memory
968 wrreq : in std_logic; port
984 -- inputs : clock, datain, wrreq, rdreq, clock
1003 elsif wrreq = '1' then -- Fifo write op's
1074 wrreq : in std_logic; port
1090 -- inputs : clock, datain, wrreq, rdreq, clock
1111 if wrreq = '1' then -- Fifo write op's
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| H A D | master_testbench3.vhdl | 163 wrreq => fifo_write,
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