| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 3811 SDValue Src1 = getValue(I.getOperand(0)); in visitShuffleVector() local
3821 EVT SrcVT = Src1.getValueType(); in visitShuffleVector()
3827 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, SrcVT.getScalarType(), Src1, in visitShuffleVector()
3842 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, Mask)); in visitShuffleVector()
3882 ConcatOps.push_back(Src1); in visitShuffleVector()
3901 MOps1[0] = Src1; in visitShuffleVector()
3904 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
3916 SDValue Result = DAG.getVectorShuffle(PaddedVT, DL, Src1, Src2, MappedOps); in visitShuffleVector()
3962 SDValue &Src = Input == 0 ? Src1 : Src2; in visitShuffleVector()
3980 setValue(&I, DAG.getVectorShuffle(VT, DL, Src1, Src2, MappedOps)); in visitShuffleVector()
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| H A D | LegalizeVectorTypes.cpp | 3118 SDValue Src1 = N->getOperand(2); in SplitVecOp_VSELECT() local
3134 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL); in SplitVecOp_VSELECT()
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| H A D | DAGCombiner.cpp | 26635 SDValue Src1 = DAG.getSplatSourceVector(N1, Index1); in scalarizeBinOpOfSplats() local
26640 if (!Src0 || !Src1 || Index0 != Index1 || in scalarizeBinOpOfSplats()
26642 Src1.getValueType().getVectorElementType() != EltVT || in scalarizeBinOpOfSplats()
26649 SDValue Y = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Src1, IndexC); in scalarizeBinOpOfSplats()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.h | 2413 Value *emitRMWOpAsInstruction(Value *Src1, Value *Src2,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 190 MachineOperand &Src1, unsigned Src1OpName) const;
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| H A D | EvergreenInstructions.td | 353 // Src1 = Offset
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| H A D | SIInstrInfo.td | 1450 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
1453 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
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| H A D | AMDGPU.td | 490 "Support SGPR for Src1 of DPP instructions"
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| H A D | AMDGPUISelLowering.cpp | 5818 auto [Dst, Src0, Src1, Src2] = MI->getFirst4Regs(); in computeNumSignBitsForTargetInstr()
5822 unsigned Tmp1 = Analysis.computeNumSignBits(Src1, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 3122 SDValue Src1 = Op.getOperand(0); in LowerADDC_ADDE_SUBC_SUBE() local
3123 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
3124 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4649 const Value *Src1 = I->getOperand(1); in selectMul() local
4652 std::swap(Src0, Src1); in selectMul()
4655 if (const auto *C = dyn_cast<ConstantInt>(Src1)) in selectMul()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 4453 const MCOperand &Src1 = Inst.getOperand(Src1Idx); in validateDPP() local
4455 if (Src1.isImm() || in validateDPP()
4456 (Src1.isReg() && isSGPR(mc2PseudoReg(Src1.getReg()), TRI))) { in validateDPP()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 1812 Register Src1 = getOrCreateVReg(*CI.getOperand(1)); in translateFixedPointIntrinsic() local
1814 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale }); in translateFixedPointIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 322 MachineInstr *emitCSINC(Register Dst, Register Src1, Register Src2,
4698 AArch64InstructionSelector::emitCSINC(Register Dst, Register Src1, in emitCSINC() argument
4714 auto CSINC = MIRBuilder.buildInstr(Opc, {Dst}, {Src1, Src2}).addImm(Pred); in emitCSINC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13216 Register Src1 = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
13237 .addReg(Src1) in EmitInstrWithCustomInserter()
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