| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ConditionalCompares.cpp | 195 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
895 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
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| H A D | AArch64CollectLOH.cpp | 289 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo(); in initReachingDef()
1030 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo(); in runOnMachineFunction()
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| H A D | AArch64PBQPRegAlloc.cpp | 331 TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); in apply()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 466 DAG.getSubtarget().getRegisterInfo()); in LowerCall()
725 DAG.getSubtarget().getRegisterInfo()); in LowerINLINEASM()
819 DAG.getSubtarget().getRegisterInfo()); in LowerDYNAMIC_STACKALLOC()
966 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); in LowerRETURNADDR()
993 DAG.getSubtarget().getRegisterInfo()); in LowerFRAMEADDR()
1458 TM.getSubtargetImpl()->getRegisterInfo()); in HexagonTargetLowering()
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| H A D | HexagonFrameLowering.cpp | 84 MF.getSubtarget().getRegisterInfo()); in emitPrologue()
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCContext.h | 192 const MCRegisterInfo *getRegisterInfo() const { return MRI; } in getRegisterInfo() function
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 338 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
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| H A D | MachineInstrBundle.cpp | 109 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in finalizeBundle()
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| H A D | MachineInstr.cpp | 288 TM ? TM->getSubtargetImpl()->getRegisterInfo() : nullptr; in print()
1621 Reg, TM->getSubtargetImpl()->getRegisterInfo(), true); in print()
1657 OS << TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIndexName( in print()
1677 TM->getSubtargetImpl()->getRegisterInfo(); in print()
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| H A D | MachineCombiner.cpp | 412 TRI = STI.getRegisterInfo(); in runOnMachineFunction()
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| H A D | RegisterScavenging.cpp | 66 TRI = MF.getSubtarget().getRegisterInfo(); in enterBasicBlock()
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| H A D | LiveRangeEdit.cpp | 421 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in calculateRegClassAndHint()
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| /minix/external/bsd/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 314 const MCRegisterInfo *MRI = DC->getRegisterInfo(); in LLVMSetDisasmOptions()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | SIInstrInfo.h | 71 const SIRegisterInfo &getRegisterInfo() const override { in getRegisterInfo() function
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| H A D | R600Packetizer.cpp | 155 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
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| H A D | SIInsertWaits.cpp | 444 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); in runOnMachineFunction()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 112 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); in emitPrologue()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 833 const TargetRegisterInfo *TRI = &getRegisterInfo(); in copyPhysReg()
937 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { in storeRegToStackSlot()
954 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { in storeRegToStackSlot()
973 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { in storeRegToStackSlot()
1129 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { in loadRegFromStackSlot()
1143 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { in loadRegFromStackSlot()
1163 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { in loadRegFromStackSlot()
1290 const TargetRegisterInfo *TRI = &getRegisterInfo(); in expandPostRAPseudo()
2414 const TargetRegisterInfo *TRI = &getRegisterInfo(); in optimizeCompareInstr()
3628 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj); in getOperandLatency()
[all …]
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| H A D | MLxExpansionPass.cpp | 382 TRI = Fn.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 228 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); in emitPrologue()
266 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(), in emitPrologue()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 1205 const MCRegisterInfo *MRI = getContext().getRegisterInfo(); in FlushUnwindOpcodes()
1298 const MCRegisterInfo *MRI = getContext().getRegisterInfo(); in emitMovSP()
1316 const MCRegisterInfo *MRI = getContext().getRegisterInfo(); in emitRegSave()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 176 const X86RegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo() function
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| H A D | X86SelectionDAGInfo.cpp | 44 DAG.getSubtarget().getRegisterInfo()); in isBaseRegConflictPossible()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.cpp | 589 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue()
885 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); in getRegisterListOpValue()
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | AsmPrinterInlineAsm.cpp | 152 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); in EmitInlineAsm()
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