| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 107 MachineOperand &Op1 = A->getOperand(1); in optimizeVccBranch() local
109 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
113 if (Op1.getReg() != ExecReg) in optimizeVccBranch()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 104 const MachineOperand &Op1 = MI->getOperand(Operand + 1); in getAddressFromInstr() local
105 AM.Scale = Op1.getImm(); in getAddressFromInstr()
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| H A D | X86ISelLowering.cpp | 19685 Op1 = DAG.getZExtOrTrunc(Op1, DL, MVT::i32); in LowerFunnelShift()
22425 Op1 = DAG.getNode(ExtendOp, dl, CmpVT, Op1); in EmitCmp()
22437 Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); in EmitCmp()
22622 Op1 = Op1.getOperand(0); in LowerAndToBT()
22871 Op1 = Op0; in LowerVSETCCWithSUBUS()
23219 Op1 = DAG.getBitcast(MVT::v4i32, Op1); in LowerVSETCC()
23253 Op1 = DAG.getBitcast(MVT::v4i32, Op1); in LowerVSETCC()
23282 Op1 = DAG.getBitcast(MVT::v4i32, Op1); in LowerVSETCC()
23306 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SM); in LowerVSETCC()
23403 if ((isOneConstant(Op1) || isNullConstant(Op1)) && in emitFlagsForSetcc()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 1754 Value *Op1; member
1757 Opcode(Opc), Op0(V0), Op1(V1) {} in BinopElts()
1796 Value *Op0 = Shuf.getOperand(0), *Op1 = Shuf.getOperand(1); in foldSelectShuffleWith1Binop() local
1799 if (match(Op0, m_BinOp(m_Specific(Op1), m_Constant(C)))) in foldSelectShuffleWith1Binop()
1809 auto *BO = cast<BinaryOperator>(Op0IsBinop ? Op0 : Op1); in foldSelectShuffleWith1Binop()
1831 Value *X = Op0IsBinop ? Op1 : Op0; in foldSelectShuffleWith1Binop()
1849 Value *Op0 = Shuf.getOperand(0), *Op1 = Shuf.getOperand(1); in canonicalizeInsertSplat() local
1930 C0 = cast<Constant>(AltB0.Op1); in foldSelectShuffle()
1934 C1 = cast<Constant>(AltB1.Op1); in foldSelectShuffle()
2085 Value *Op0 = Shuf.getOperand(0), *Op1 = Shuf.getOperand(1); in foldIdentityExtractShuffle() local
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreSelectionDAGInfo.h | 23 SDValue Chain, SDValue Op1, SDValue Op2,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SelectionDAGInfo.h | 28 SDValue Chain, SDValue Op1, SDValue Op2,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 933 MachineOperand Op1 = MI.getOperand(1); in simplifyCode() local
935 if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2)) in simplifyCode()
936 std::swap(Op1, Op2); in simplifyCode()
937 else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1)) in simplifyCode()
949 MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI); in simplifyCode()
979 .add(Op1); in simplifyCode()
1463 Register Op1 = CMPI2->getOperand(1).getReg(); in eliminateRedundantCompare() local
1466 CMPI2->getOperand(2).setReg(Op1); in eliminateRedundantCompare()
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| H A D | PPCISelDAGToDAG.cpp | 780 SDValue Op1 = N->getOperand(1); in tryBitfieldInsert() local
803 std::swap(Op0, Op1); in tryBitfieldInsert()
811 std::swap(Op0, Op1); in tryBitfieldInsert()
821 Op1 = Op1.getOperand(0); in tryBitfieldInsert()
836 Op1 = Op1.getOperand(0).getOperand(0); in tryBitfieldInsert()
5329 SDValue Op1 = N->getOperand(1); in Select() local
5330 if (Op1.getOpcode() != ISD::Constant || Op1.getValueType() != MVT::i64) in Select()
5537 std::swap(Op1, Op2); in Select()
5866 Op1 = Op1.getOperand(0); in combineToCMPB()
5879 RHS = Op1.getOperand(0); in combineToCMPB()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelDAGToDAG.cpp | 284 SDValue Op0, Op1; in SelectInlineAsmMemoryOperand() local
288 if (!SelectAddr(Op, Op0, Op1)) in SelectInlineAsmMemoryOperand()
294 OutOps.push_back(Op1); in SelectInlineAsmMemoryOperand()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 269 BPFOperand &Op1 = (BPFOperand &)*Operands[1]; in PreMatchCheck() local
272 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
273 && Op1.getToken() == "=" in PreMatchCheck()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | Reassociate.cpp | 2403 Value *Op1 = Ops[j].Op; in ReassociateExpression() local
2404 if (std::less<Value *>()(Op1, Op0)) in ReassociateExpression()
2405 std::swap(Op0, Op1); in ReassociateExpression()
2406 auto it = PairMap[Idx].find({Op0, Op1}); in ReassociateExpression()
2426 auto Op1 = Ops[BestPair.second]; in ReassociateExpression() local
2430 Ops.push_back(Op1); in ReassociateExpression()
2479 Value *Op1 = Ops[j]; in BuildPairMap() local
2480 if (std::less<Value *>()(Op1, Op0)) in BuildPairMap()
2481 std::swap(Op0, Op1); in BuildPairMap()
2482 if (!Visited.insert({Op0, Op1}).second) in BuildPairMap()
[all …]
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| H A D | NaryReassociate.cpp | 522 Value *&Op1, Value *&Op2) { in matchTernaryOp() argument
525 return match(V, m_Add(m_Value(Op1), m_Value(Op2))); in matchTernaryOp()
527 return match(V, m_Mul(m_Value(Op1), m_Value(Op2))); in matchTernaryOp()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Utils/ |
| H A D | BuildLibCalls.h | 171 Value *emitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name,
176 Value *emitBinaryFloatFnCall(Value *Op1, Value *Op2,
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfoImpl.h | 1028 const Value *Op0, *Op1; in getUserCost() local
1029 if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) || in getUserCost()
1030 match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) { in getUserCost()
1036 TTI::OperandValueKind Op2VK = TTI::getOperandInfo(Op1, Op2VP); in getUserCost()
1038 Op1->getType()->getScalarSizeInBits() == 1); in getUserCost()
1040 SmallVector<const Value *, 2> Operands{Op0, Op1}; in getUserCost()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1423 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type);
1428 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type);
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| H A D | SelectionDAGAddressAnalysis.h | 82 const SDNode *Op1,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGAddressAnalysis.cpp | 88 const SDNode *Op1, in computeAliasing() argument
93 BaseIndexOffset BasePtr1 = match(Op1, DAG); in computeAliasing()
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| H A D | SelectionDAG.cpp | 1095 SDValue Ops[] = { Op1, Op2 }; in FindModifiedNodeSlot()
8195 if (N->OperandList[0] != Op1) in UpdateNodeOperands()
8196 N->OperandList[0].set(Op1); in UpdateNodeOperands()
8301 SDValue Ops[] = { Op1 }; in SelectNodeTo()
8309 SDValue Ops[] = { Op1, Op2 }; in SelectNodeTo()
8350 SDValue Ops[] = { Op1, Op2 }; in SelectNodeTo()
8509 SDValue Ops[] = { Op1 }; in getMachineNode()
8516 SDValue Ops[] = { Op1, Op2 }; in getMachineNode()
8538 SDValue Ops[] = { Op1, Op2 }; in getMachineNode()
8561 SDValue Ops[] = { Op1, Op2 }; in getMachineNode()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 489 SDValue Op1 = N->getOperand(1); in performANDCombine() local
609 SDValue Op1 = N->getOperand(1); in performORCombine() local
614 SDValue Op1Op0 = Op1->getOperand(0); in performORCombine()
900 SDValue Op1 = N->getOperand(1); in performSRACombine() local
1007 SDValue Op1 = N->getOperand(1); in performXORCombine() local
1011 NotOp = Op1; in performXORCombine()
2420 SDValue Op1 = Op->getOperand(1); in lowerEXTRACT_VECTOR_ELT() local
2938 SDValue Op1; in lowerVECTOR_SHUFFLE_VSHF() local
2964 Op1 = Op->getOperand(1); in lowerVECTOR_SHUFFLE_VSHF()
2966 Op0 = Op1 = Op->getOperand(0); in lowerVECTOR_SHUFFLE_VSHF()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 56 SDValue Chain, SDValue Op1, SDValue Op2,
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| H A D | BuildLibCalls.cpp | 1485 static Value *emitBinaryFloatFnCallHelper(Value *Op1, Value *Op2, in emitBinaryFloatFnCallHelper() argument
1492 FunctionCallee Callee = M->getOrInsertFunction(Name, Op1->getType(), in emitBinaryFloatFnCallHelper()
1493 Op1->getType(), Op2->getType()); in emitBinaryFloatFnCallHelper()
1496 CallInst *CI = B.CreateCall(Callee, { Op1, Op2 }, Name); in emitBinaryFloatFnCallHelper()
1511 Value *llvm::emitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name, in emitBinaryFloatFnCall() argument
1517 appendTypeSuffix(Op1, Name, NameBuffer); in emitBinaryFloatFnCall()
1519 return emitBinaryFloatFnCallHelper(Op1, Op2, Name, B, Attrs); in emitBinaryFloatFnCall()
1522 Value *llvm::emitBinaryFloatFnCall(Value *Op1, Value *Op2, in emitBinaryFloatFnCall() argument
1528 StringRef Name = getFloatFnName(TLI, Op1->getType(), in emitBinaryFloatFnCall()
1531 return emitBinaryFloatFnCallHelper(Op1, Op2, Name, B, Attrs, TLI); in emitBinaryFloatFnCall()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1906 SDValue Op1 = N->getOperand(1); in balanceSubTree() local
1910 (!isOpcodeHandled(Op1.getNode()) || RootWeights.count(Op1.getNode()))) { in balanceSubTree()
1961 (isOpcodeHandled(Op1.getNode()) && Op1.getOpcode() == ISD::SHL && in balanceSubTree()
1962 Op1.getConstantOperandVal(1) < 4))) in balanceSubTree()
2034 SDValue Op1; in balanceSubTree() local
2036 Op1 = getMultiplierForSHL(Child.getNode()); in balanceSubTree()
2038 Op1 = Child->getOperand(1); in balanceSubTree()
2040 if (!NodeHeights.count(Op1) || !NodeHeights.count(Child->getOperand(0))) { in balanceSubTree()
2044 Worklist.push_back(Op1); in balanceSubTree()
2048 if (std::abs(NodeHeights[Op1] - NodeHeights[Child->getOperand(0)]) > 1) in balanceSubTree()
[all …]
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| H A D | HexagonISelLowering.cpp | 1093 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2); in LowerVSELECT() local
1094 MVT OpTy = ty(Op1); in LowerVSELECT()
1105 DAG.getSExtOrTrunc(Op1, dl, WideTy), in LowerVSELECT()
2126 SDValue Op1 = Addr.getOperand(1); in getBaseAndOffset() local
2149 SDValue Op1 = Op.getOperand(1); in LowerVECTOR_SHUFFLE() local
2155 if (ty(Op0) != VecTy || ty(Op1) != VecTy) in LowerVECTOR_SHUFFLE()
2166 std::swap(Op0, Op1); in LowerVECTOR_SHUFFLE()
2212 typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0}); in LowerVECTOR_SHUFFLE()
2219 typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1}); in LowerVECTOR_SHUFFLE()
2281 SDValue Op1 = Op.getOperand(1); in getVectorShiftByInt() local
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 1179 Op1 = Op0; in UpgradeX86ALIGNIntrinsics()
1266 Value *Op1 = CI.getOperand(1); in UpgradeX86BinaryIntrinsics() local
1348 Value *Op1 = CI.getArgOperand(1); in upgradeX86ConcatShift() local
1352 std::swap(Op0, Op1); in upgradeX86ConcatShift()
1982 Value *Op1 = CI->getArgOperand(1); in UpgradeIntrinsicCall() local
1984 Rep = Builder.CreateAnd(Op0, Op1); in UpgradeIntrinsicCall()
2581 Value *Op1 = CI->getArgOperand(1); in UpgradeIntrinsicCall() local
2595 Value *Op1 = CI->getArgOperand(1); in UpgradeIntrinsicCall() local
2780 Value *Op1 = CI->getArgOperand(1); in UpgradeIntrinsicCall() local
2828 Value *Op1 = CI->getArgOperand(1); in UpgradeIntrinsicCall() local
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFISelDAGToDAG.cpp | 162 SDValue Op0, Op1; in SelectInlineAsmMemoryOperand() local
167 if (!SelectAddr(Op, Op0, Op1)) in SelectInlineAsmMemoryOperand()
175 OutOps.push_back(Op1); in SelectInlineAsmMemoryOperand()
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