| /netbsd/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | Verifier.cpp | 511 void visitReturnInst(ReturnInst &RI);
530 void visitResumeInst(ResumeInst &RI);
2743 Function *F = RI.getParent()->getParent(); in visitReturnInst()
2744 unsigned N = RI.getNumOperands(); in visitReturnInst()
2749 &RI, F->getReturnType()); in visitReturnInst()
2754 &RI, F->getReturnType()); in visitReturnInst()
2758 visitTerminator(RI); in visitReturnInst()
4023 &RI); in visitResumeInst()
4025 visitTerminator(RI); in visitResumeInst()
5090 Assert(RI, in visitIntrinsicCall()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 132 const X86RegisterInfo RI; variable
149 const X86RegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo()
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| H A D | X86InstrControl.td | 37 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
197 def FARJMP64m : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
359 def FARCALL64m : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
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| H A D | X86InstrInfo.cpp | 86 Subtarget(STI), RI(STI.getTargetTriple()) { in X86InstrInfo()
3523 << RI.getName(DestReg) << '\n'); in copyPhysReg()
4245 RI = ++I.getReverse(), in optimizeCompareInstr() local
4250 for (; RI != RE; ++RI) { in optimizeCompareInstr()
4251 MachineInstr &Instr = *RI; in optimizeCompareInstr()
4801 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit); in expandPostRAPseudo()
5585 &RI, MF); in foldMemoryOperandImpl()
5717 if (!RI.hasStackRealignment(MF)) in foldMemoryOperandImpl()
6466 DstRC = getRegClass(MCID, 0, &RI, MF); in unfoldMemoryOperand()
9017 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) || in getOutliningType()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrFormats.td | 28 // Register Immediate (RI)
59 // If and only if the `F' bit is 1, RI instructions modify the
73 // otherwise. For other RI instructions, `V' is cleared.
131 // instructions in *Note RI::). For the SELECT operation, Rd gets Rs1 if
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | CorrelatedValuePropagation.cpp | 1079 auto *RI = cast<ReturnInst>(Term); in runImpl() local
1083 auto *RetVal = RI->getReturnValue(); in runImpl()
1086 if (auto *C = getConstantAt(RetVal, RI, LVI)) { in runImpl()
1088 RI->replaceUsesOfWith(RetVal, C); in runImpl()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMachineCFGStructurizer.cpp | 739 for (auto &RI : II.defs()) { in storeLiveOuts() local
740 storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo); in storeLiveOuts()
781 for (auto &RI : II.defs()) { in storeMBBLiveOuts() local
782 storeLiveOutRegRegion(TopRegion, RI.getReg(), RI.getParent(), MRI, TRI, in storeMBBLiveOuts()
1007 for (auto &RI : II.uses()) { in removeFalseRegisterKills() local
1008 if (RI.isReg()) { in removeFalseRegisterKills()
1009 Register Reg = RI.getReg(); in removeFalseRegisterKills()
1030 MachineOperand *UseOperand = &(RI); in removeFalseRegisterKills()
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| H A D | SIFrameLowering.cpp | 1117 const SIRegisterInfo *RI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in getFrameIndexReference() local
1119 FrameReg = RI->getFrameRegister(MF); in getFrameIndexReference()
1249 const SIRegisterInfo *RI = ST.getRegisterInfo(); in assignCalleeSavedSpillSlots() local
1251 Register BasePtrReg = RI->getBaseRegister(); in assignCalleeSavedSpillSlots()
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| /netbsd/external/gpl3/gcc/dist/gcc/config/s390/ |
| H A D | s390.md | 939 [(set_attr "op_type" "RI")
952 [(set_attr "op_type" "RI")
961 [(set_attr "op_type" "RI")
1910 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RRE,RXY,RIL,RRE,RXY,
2227 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
4655 [(set_attr "op_type" "RI")
7627 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7754 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
8033 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
8112 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
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| /netbsd/external/apache2/llvm/dist/clang/utils/TableGen/ |
| H A D | ClangDiagnosticsEmitter.cpp | 1361 std::map<std::string, GroupInfo>::const_iterator RI = in emitDiagSubGroups() local
1363 assert(RI != DiagsInGroup.end() && "Referenced without existing?"); in emitDiagSubGroups()
1364 OS << RI->second.IDNo << ", "; in emitDiagSubGroups()
1371 std::map<std::string, GroupInfo>::const_iterator RI = in emitDiagSubGroups() local
1373 assert(RI != DiagsInGroup.end() && "Referenced without existing?"); in emitDiagSubGroups()
1374 OS << RI->second.IDNo << ", "; in emitDiagSubGroups()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | SjLjEHPrepare.cpp | 381 } else if (auto *RI = dyn_cast<ReturnInst>(BB.getTerminator())) { in setupEntryBlockAndCallSites() local
382 Returns.push_back(RI); in setupEntryBlockAndCallSites()
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| H A D | MachineSink.cpp | 1693 for (auto RI = MCRegUnitIterator(Reg, TRI); RI.isValid(); ++RI) in getRegUnits() local
1694 RegUnits.insert(*RI); in getRegUnits()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 310 const MCRegisterInfo *RI) { in getPairedGPR() argument
311 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) in getPairedGPR()
313 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); in getPairedGPR()
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| H A D | Thumb1InstrInfo.cpp | 24 : ARMBaseInstrInfo(STI), RI() {} in Thumb1InstrInfo()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 952 Value *RI = Builder.CreateBinOp(BO->getOpcode(), Op0, Op1, in foldOperationIntoSelectOperand() local
954 auto *FPInst = dyn_cast<Instruction>(RI); in foldOperationIntoSelectOperand()
957 return RI; in foldOperationIntoSelectOperand()
1049 Value *RI = Builder.CreateBinOp(I->getOpcode(), Op0, Op1, "phi.bo"); in foldOperationIntoPhiValue() local
1050 auto *FPInst = dyn_cast<Instruction>(RI); in foldOperationIntoPhiValue()
1053 return RI; in foldOperationIntoPhiValue()
2828 Instruction *InstCombinerImpl::visitReturnInst(ReturnInst &RI) { in visitReturnInst() argument
2829 if (RI.getNumOperands() == 0) // ret void in visitReturnInst()
2832 Value *ResultOp = RI.getOperand(0); in visitReturnInst()
2843 KnownBits Known = computeKnownBits(ResultOp, 0, &RI); in visitReturnInst()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.cpp | 39 RI(STI.getTargetTriple()) {} in WebAssemblyInstrInfo()
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| /netbsd/external/apache2/llvm/dist/clang/lib/Sema/ |
| H A D | SemaStmt.cpp | 1491 for (CaseRangesTy::const_iterator RI = CaseRanges.begin(); in ActOnFinishSwitchStmt() local
1492 RI != CaseRanges.end(); RI++) { in ActOnFinishSwitchStmt()
1493 Expr *CaseExpr = RI->second->getLHS(); in ActOnFinishSwitchStmt()
1495 RI->first)) in ActOnFinishSwitchStmt()
1500 RI->second->getRHS()->EvaluateKnownConstInt(Context); in ActOnFinishSwitchStmt()
1503 CaseExpr = RI->second->getRHS(); in ActOnFinishSwitchStmt()
1512 auto RI = CaseRanges.begin(); in ActOnFinishSwitchStmt() local
1543 for (; RI != CaseRanges.end(); RI++) { in ActOnFinishSwitchStmt()
1545 RI->second->getRHS()->EvaluateKnownConstInt(Context); in ActOnFinishSwitchStmt()
1551 if (RI == CaseRanges.end() || EI->first < RI->first) { in ActOnFinishSwitchStmt()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 188 const PPCRegisterInfo RI; variable
284 const PPCRegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | InlineCost.cpp | 402 bool visitReturnInst(ReturnInst &RI);
407 bool visitResumeInst(ResumeInst &RI);
408 bool visitCleanupReturnInst(CleanupReturnInst &RI);
409 bool visitCatchReturnInst(CatchReturnInst &RI);
1895 bool CallAnalyzer::visitReturnInst(ReturnInst &RI) { in visitReturnInst() argument
2032 bool CallAnalyzer::visitResumeInst(ResumeInst &RI) { in visitResumeInst() argument
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 197 MachineBasicBlock::reverse_iterator RI(LastLocalValue); in flushLocalValueMap() local
198 for (; RI != RE;) { in flushLocalValueMap()
199 MachineInstr &LocalMI = *RI; in flushLocalValueMap()
201 ++RI; in flushLocalValueMap()
2232 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg); in tryToFoldLoad() local
2233 MachineInstr *User = RI->getParent(); in tryToFoldLoad()
2242 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI); in tryToFoldLoad()
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| /netbsd/share/misc/ |
| H A D | na.postal | 74 RI:Rhode Island:R.I.:US
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 382 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo(); in emitFrameDirective() local
384 Register stackReg = RI.getFrameRegister(*MF); in emitFrameDirective()
385 unsigned returnReg = RI.getRARegister(); in emitFrameDirective()
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| /netbsd/games/quiz/datfiles/ |
| H A D | areas | 35 401:rhode island|RI:
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| /netbsd/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 1288 const RegSizeInfo &RI = RC.RSI.get(M); in runTargetDesc() local
1289 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1290 << RI.SpillAlignment; in runTargetDesc()
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| /netbsd/external/bsd/libbind/dist/doc/ |
| H A D | getnameinfo.cat3 | 14 DDEESSCCRRIIPPTTIIOONN
|