| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
118 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
119 return Reg; in getDefReg()
124 return Reg; in getDefReg()
128 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
129 return Reg; in getDefReg()
132 return Reg; in getDefReg()
135 return Reg; in getDefReg()
165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RDFRegisters.cpp | 49 if (UnitInfos[U].Reg != 0) in PhysicalRegisterInfo()
57 UnitInfos[U].Reg = F; in PhysicalRegisterInfo()
62 UI.Reg = F; in PhysicalRegisterInfo()
109 assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg)); in getAliasSet()
110 if (isRegMaskId(Reg)) { in getAliasSet()
120 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
168 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); in aliasRM()
170 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); in aliasRM()
203 assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); in aliasMM()
231 if (RR.Reg == R) in mapTo()
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| H A D | CalcSpillWeights.cpp | 39 if (MRI.reg_nodbg_empty(Reg)) in calculateSpillWeightsAndHints()
51 if (MI->getOperand(0).getReg() == Reg) { in copyHint()
83 unsigned Reg = LI.reg(); in isRematerializable() local
84 unsigned Original = VRM.getOriginal(Reg); in isRematerializable()
105 Reg = MI->getOperand(1).getReg(); in isRematerializable()
109 if (!Register::isVirtualRegister(Reg) || VRM.getOriginal(Reg) != Original) in isRematerializable()
167 Register Reg = LI.reg(); in weightCalcHelper() local
203 const Register Reg; in weightCalcHelper() member
208 if (Reg.isPhysical() != Rhs.Reg.isPhysical()) in weightCalcHelper()
209 return Reg.isPhysical(); in weightCalcHelper()
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| H A D | RegAllocFast.cpp | 696 if (Reg.isPhysical()) in traceCopyChain()
697 return Reg; in traceCopyChain()
717 Reg = traceCopyChain(Reg); in traceCopies()
718 if (Reg.isValid()) in traceCopies()
719 return Reg; in traceCopies()
1063 if (Reg.isVirtual()) { in addRegClassDefCounts()
1265 if (!Reg) in allocateInstruction()
1270 freePhysReg(Reg); in allocateInstruction()
1324 mayLiveIn(Reg); in allocateInstruction()
1362 if (!Reg) in allocateInstruction()
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| H A D | RegisterPressure.cpp | 502 Register Reg = MO.getReg(); in collectOperand() local
520 void pushReg(Register Reg, in pushReg() argument
522 if (Reg.isVirtual()) { in pushReg()
534 Register Reg = MO.getReg(); in collectOperandLanes() local
555 if (Reg.isVirtual()) { in pushRegLanes()
585 Register Reg = RI->RegUnit; in detectDeadDefs() local
747 Register Reg = P.RegUnit; in bumpDeadDefs() local
753 Register Reg = P.RegUnit; in bumpDeadDefs() local
775 Register Reg = Def.RegUnit; in recede() local
1065 Register Reg = P.RegUnit; in bumpUpwardPressure() local
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| H A D | TargetRegisterInfo.cpp | 90 if (Checked[Reg]) in checkAllSuperRegsMarked()
113 if (!Reg) in printReg()
125 OS << '$' << "physreg" << Reg; in printReg()
126 else if (Reg < TRI->getNumRegs()) { in printReg()
183 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && in printRegClassOrBank()
432 for (auto Reg : Hints_MRI.second) { in getRegAllocationHints() local
439 Register Phys = Reg; in getRegAllocationHints()
504 if (Reg.isPhysical()) { in getRegSizeInBits()
508 RC = getMinimalPhysRegClass(Reg); in getRegSizeInBits()
510 LLT Ty = MRI.getType(Reg); in getRegSizeInBits()
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| H A D | PeepholeOptimizer.cpp | 298 addSource(Reg, SubReg); in ValueTrackerResult()
379 Register Reg; member in __anond81e010a0111::ValueTracker
424 : DefSubReg(DefSubReg), Reg(Reg), MRI(MRI), TII(TII) { in ValueTracker()
671 Register Reg = RegSubReg.Reg; in findNextSource() local
672 if (Reg.isPhysical()) in findNextSource()
752 return CurSrcPair.Reg != Reg; in findNextSource()
1203 if (Src.Reg == NewSrc.Reg || NewSrc.Reg == 0) in optimizeCoalescableCopy()
1346 if (Reg.isVirtual()) { in isMoveImmediate()
1348 ImmDefRegs.insert(Reg); in isMoveImmediate()
1366 if (!Reg.isVirtual()) in foldImmediate()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1176 switch (Reg) { in getNextVectorRegister()
1251 return Reg; in getNextVectorRegister()
1297 Reg = FirstReg; in printVectorList()
1299 Reg = FirstReg; in printVectorList()
1301 Reg = FirstReg; in printVectorList()
1308 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); in printVectorList()
1311 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { in printVectorList()
1460 if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) in printMRSSystemRegister()
1461 O << Reg->Name; in printMRSSystemRegister()
1486 if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) in printMSRSystemRegister()
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| H A D | AArch64WinCOFFStreamer.cpp | 69 int Reg, in EmitARM64WinUnwindCode() argument
76 auto Inst = WinEH::Instruction(UnwindCode, Label, Reg, Offset); in EmitARM64WinUnwindCode()
108 EmitARM64WinUnwindCode(Win64EH::UOP_SaveReg, Reg, Offset); in EmitARM64WinCFISaveReg()
113 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegX, Reg, Offset); in EmitARM64WinCFISaveRegX()
118 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegP, Reg, Offset); in EmitARM64WinCFISaveRegP()
123 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegPX, Reg, Offset); in EmitARM64WinCFISaveRegPX()
128 EmitARM64WinUnwindCode(Win64EH::UOP_SaveLRPair, Reg, Offset); in EmitARM64WinCFISaveLRPair()
135 EmitARM64WinUnwindCode(Win64EH::UOP_SaveFReg, Reg, Offset); in EmitARM64WinCFISaveFReg()
140 EmitARM64WinUnwindCode(Win64EH::UOP_SaveFRegX, Reg, Offset); in EmitARM64WinCFISaveFRegX()
145 EmitARM64WinUnwindCode(Win64EH::UOP_SaveFRegP, Reg, Offset); in EmitARM64WinCFISaveFRegP()
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| H A D | AArch64ELFStreamer.cpp | 68 void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) override { in EmitARM64WinCFISaveReg() argument
69 OS << "\t.seh_save_reg\tx" << Reg << ", " << Offset << "\n"; in EmitARM64WinCFISaveReg()
71 void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) override { in EmitARM64WinCFISaveRegX() argument
72 OS << "\t.seh_save_reg_x\tx" << Reg << ", " << Offset << "\n"; in EmitARM64WinCFISaveRegX()
74 void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) override { in EmitARM64WinCFISaveRegP() argument
75 OS << "\t.seh_save_regp\tx" << Reg << ", " << Offset << "\n"; in EmitARM64WinCFISaveRegP()
78 OS << "\t.seh_save_regp_x\tx" << Reg << ", " << Offset << "\n"; in EmitARM64WinCFISaveRegPX()
81 OS << "\t.seh_save_lrpair\tx" << Reg << ", " << Offset << "\n"; in EmitARM64WinCFISaveLRPair()
83 void EmitARM64WinCFISaveFReg(unsigned Reg, int Offset) override { in EmitARM64WinCFISaveFReg() argument
84 OS << "\t.seh_save_freg\td" << Reg << ", " << Offset << "\n"; in EmitARM64WinCFISaveFReg()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | LiveIntervals.h | 115 if (hasInterval(Reg)) in getInterval()
116 return *VirtRegIntervals[Reg.id()]; in getInterval()
125 bool hasInterval(Register Reg) const { in hasInterval() argument
127 VirtRegIntervals[Reg.id()]; in hasInterval()
133 VirtRegIntervals.grow(Reg.id()); in createEmptyInterval()
134 VirtRegIntervals[Reg.id()] = createInterval(Reg); in createEmptyInterval()
135 return *VirtRegIntervals[Reg.id()]; in createEmptyInterval()
145 void removeInterval(Register Reg) { in removeInterval() argument
146 delete VirtRegIntervals[Reg]; in removeInterval()
147 VirtRegIntervals[Reg] = nullptr; in removeInterval()
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| H A D | LiveRegUnits.h | 56 Register Reg = O->getReg(); in accumulateUsedDefed() local
57 if (!Reg.isPhysical()) in accumulateUsedDefed()
63 if (!TRI->isConstantPhysReg(Reg)) in accumulateUsedDefed()
64 ModifiedRegUnits.addReg(Reg); in accumulateUsedDefed()
67 UsedRegUnits.addReg(Reg); in accumulateUsedDefed()
86 void addReg(MCPhysReg Reg) { in addReg() argument
87 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) in addReg()
93 void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) { in addRegMasked() argument
102 void removeReg(MCPhysReg Reg) { in removeReg() argument
103 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) in removeReg()
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| /netbsd/external/gpl3/gdb/dist/sim/arm/ |
| H A D | armemu.c | 309 state->Reg[Rd] = val; in handle_v6_insn()
703 state->Reg[Rd] = res; in handle_v6_insn()
828 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; in handle_v6_insn()
869 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; in handle_v6_insn()
914 state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; in handle_v6_insn()
1037 val = state->Reg[Rn]; in handle_v6_insn()
1041 state->Reg[Rd] = val; in handle_v6_insn()
1630 state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs; in ARMul_Emulate32()
1709 state->Reg[MULDESTReg] = state->Reg[MULACCReg]; in ARMul_Emulate32()
1713 state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; in ARMul_Emulate32()
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| H A D | armemu.h | 150 #define PC (state->Reg[15] & PCMASK)
156 #define R15PC (state->Reg[15] & R15PCBITS)
210 state->Reg[14] = temp - (d); \
274 state->Reg[15] += isize; \
288 state->Reg[15] += isize; \
298 state->Reg[15] += isize; \
319 #define DEST (state->Reg[DESTReg])
323 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
325 #define LHS (state->Reg[LHSReg])
354 #define LSBase state->Reg[LHSReg]
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| /netbsd/external/gpl3/gdb.old/dist/sim/arm/ |
| H A D | armemu.c | 309 state->Reg[Rd] = val; in handle_v6_insn()
703 state->Reg[Rd] = res; in handle_v6_insn()
828 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; in handle_v6_insn()
869 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; in handle_v6_insn()
914 state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; in handle_v6_insn()
1037 val = state->Reg[Rn]; in handle_v6_insn()
1041 state->Reg[Rd] = val; in handle_v6_insn()
1630 state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs; in ARMul_Emulate32()
1709 state->Reg[MULDESTReg] = state->Reg[MULACCReg]; in ARMul_Emulate32()
1713 state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; in ARMul_Emulate32()
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| H A D | armemu.h | 150 #define PC (state->Reg[15] & PCMASK)
156 #define R15PC (state->Reg[15] & R15PCBITS)
210 state->Reg[14] = temp - (d); \
274 state->Reg[15] += isize; \
288 state->Reg[15] += isize; \
298 state->Reg[15] += isize; \
319 #define DEST (state->Reg[DESTReg])
323 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
325 #define LHS (state->Reg[LHSReg])
354 #define LSBase state->Reg[LHSReg]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 56 RegisterSubReg(const Register &Reg) : R(Reg), S(0) {} in RegisterSubReg()
59 return R == Reg.R && S == Reg.S; in operator ==()
63 return R < Reg.R || (R == Reg.R && S < Reg.S); in operator <()
73 RegisterSubReg Reg; member
80 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
228 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n"); in processPredicateGPR()
233 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); in processPredicateGPR()
250 assert(Reg.R.isVirtual()); in getPredRegFor()
277 .addReg(Reg.R, 0, Reg.S); in getPredRegFor()
379 RegisterSubReg Reg(MO); in convertToPredForm() local
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| H A D | HexagonExpandCondsets.cpp | 184 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
188 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
191 Register Reg; member
290 assert(Reg.isVirtual()); in getLaneMask()
369 assert(Reg.isVirtual()); in updateDeadsInRange()
538 updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI); in updateDeadFlags()
592 PhysR = RS.Reg; in getCondTfrOpcode()
774 if (RR.Reg != RD.Reg) in getReachingDefForPred()
925 Op.setReg(RN.Reg); in renameInRange()
1096 if (!RR.Reg.isVirtual()) in isIntReg()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 287 if (MRI.hasOneUse(Reg)) in hasOneUse()
367 Register Reg = MO.getReg(); in isSafeToMove() local
371 !Insert->readsRegister(Reg)) in isSafeToMove()
380 if (!MRI.isPhysRegModified(Reg)) in isSafeToMove()
525 if (MRI.hasOneDef(Reg) && MRI.hasOneUse(Reg)) { in moveForSingleUse()
528 MFI.stackifyVReg(MRI, Reg); in moveForSingleUse()
580 bool IsDead = MRI.use_empty(Reg); in rematerializeCheapDef()
593 LIS.removeInterval(Reg); in rematerializeCheapDef()
839 Register Reg = Use.getReg(); in runOnMachineFunction() local
958 Register Reg = MO.getReg(); in runOnMachineFunction() local
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| H A D | WebAssemblyFastISel.cpp | 59 unsigned Reg; member
83 Base.Reg = Reg; in setReg()
373 if (Reg == 0) in computeAddress()
434 if (Reg == 0) in getRegForI1Value()
441 if (Reg == 0) in zeroExtendToI32()
477 if (Reg == 0) in signExtendToI32()
518 Reg = zeroExtendToI32(Reg, V, From); in zeroExtend()
540 Reg = signExtendToI32(Reg, V, From); in signExtend()
975 if (Reg == 0) in selectTrunc()
1000 if (Reg == 0) in selectZExt()
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| /netbsd/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/ |
| H A D | Target.cpp | 90 .addReg(Reg) in loadImmediate()
103 .addReg(Reg) in loadImmediate()
108 .addReg(Reg) in loadImmediate()
109 .addReg(Reg) in loadImmediate()
114 .addReg(Reg) in loadImmediate()
122 .addReg(Reg) in loadImmediate()
138 unsigned Reg, in fillMemoryOperands() argument
150 if (Mips::GPR32RegClass.contains(Reg)) in setRegTo()
151 return loadImmediate(Reg, true, Value); in setRegTo()
152 if (Mips::GPR64RegClass.contains(Reg)) in setRegTo()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 122 unsigned Reg; member
135 RegOp Reg; member
172 Op->Reg.Num = Num; in createReg()
227 return Reg.Num; in getReg()
805 Register Reg; in parseRegister() local
850 if (Reg.Group != RegV && Reg.Group != RegFP) { in parseRegister()
886 SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc)); in parseRegister()
918 Register Reg; in parseAnyRegister() local
981 Reg.Group = Group; in parseIntegerRegister()
1327 Register Reg; in ParseRegister() local
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| /netbsd/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | ValistChecker.cpp | 74 : Reg(Reg), IsLeak(IsLeak) {} in ValistBugVisitor()
78 ID.AddPointer(Reg); in Profile()
96 const MemRegion *Reg; member in __anon659acd970111::ValistChecker::ValistBugVisitor
166 const MemRegion *Reg = SV.getAsRegion(); in getVAListAsRegion() local
167 if (!Reg) in getVAListAsRegion()
180 IsSymbolic = Reg && Reg->getAs<SymbolicRegion>(); in getVAListAsRegion()
208 for (auto Reg : TrackedVALists) { in checkDeadSymbols() local
209 if (SR.isLiveRegion(Reg)) in checkDeadSymbols()
211 LeakedVALists.push_back(Reg); in checkDeadSymbols()
272 for (auto Reg : LeakedVALists) { in reportLeakedVALists() local
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 53 if (Register::isVirtualRegister(Reg)) { in IsRegInClass()
54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
55 } else if (RC->contains(Reg)) { in IsRegInClass()
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
63 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
67 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
71 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
75 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 31 if (!LIS.hasInterval(Reg)) in printLivesAt()
74 assert(Reg.isVirtual()); in getRegKind()
230 auto Reg = MO.getReg(); in collectVirtualRegUses() local
232 Res, [Reg](const RegisterMaskPair &RM) { return RM.RegUnit == Reg; }); in collectVirtualRegUses()
269 if (!LIS.hasInterval(Reg)) in getLiveRegs()
273 LiveRegs[Reg] = LiveMask; in getLiveRegs()
322 auto Reg = MO.getReg(); in recede() local
323 auto I = LiveRegs.find(Reg); in recede()
398 Register Reg = MO.getReg(); in advanceToNext() local
399 if (!Reg.isVirtual()) in advanceToNext()
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