/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 211 switch (Reg) { in emitPrologue() 273 switch (Reg) { in emitPrologue() 354 switch (Reg) { in emitPrologue() 381 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { in emitPrologue() 536 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { in emitEpilogue() 597 TmpReg = Reg; in findTemporariesForLR() 829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in spillCalleeSavedRegisters() 831 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in spillCalleeSavedRegisters() 837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters() 953 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in restoreCalleeSavedRegisters() [all …]
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H A D | ARMFrameLowering.cpp | 494 switch (Reg) { in emitPrologue() 716 switch (Reg) { in emitPrologue() 749 switch (Reg) { in emitPrologue() 776 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && in emitPrologue() 1093 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPushInst() 1105 LastReg = Reg; in emitPushInst() 1185 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) in emitPopInst() 1208 LastReg = Reg; in emitPopInst() 2137 if (Reg != ARM::LR && !MRI.isPhysRegUsed(Reg)) in determineCalleeSaves() 2185 if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg) && in determineCalleeSaves() [all …]
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H A D | ARMCallingConv.cpp | 27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS() local 41 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS() local 71 if (Reg == 0) { in f64AssignAAPCS() 74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS() 75 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); in f64AssignAAPCS() 89 if (HiRegList[i] == Reg) in f64AssignAAPCS() 120 if (Reg == 0) in f64RetAssign() 125 if (HiRegList[i] == Reg) in f64RetAssign() 265 for (auto Reg : RegList) in CC_ARM_AAPCS_Custom_Aggregate() local 266 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | MachineCopyPropagation.cpp | 102 for (MCRegister Reg : Regs) { in markRegsUnavailable() local 118 RegsToInvalidate.insert(Reg); in invalidateRegister() 202 MCRegUnitIterator RUI(Reg, &TRI); in findAvailBackwardCopy() 225 MCRegUnitIterator RUI(Reg, &TRI); in findAvailCopy() 618 if (!Reg) in ForwardCopyPropagateBlock() 641 if (!Reg) in ForwardCopyPropagateBlock() 673 Register Reg = MO.getReg(); in ForwardCopyPropagateBlock() local 674 if (!Reg) in ForwardCopyPropagateBlock() 677 assert(!Reg.isVirtual() && in ForwardCopyPropagateBlock() 721 for (MCRegister Reg : Defs) in ForwardCopyPropagateBlock() local [all …]
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H A D | TwoAddressInstructionPass.cpp | 336 if (Reg.isPhysical() && (allowFalsePositives || MRI->hasOneUse(Reg))) in isKilled() 340 if (Reg.isPhysical()) in isKilled() 354 Reg = SrcReg; in isKilled() 404 while (Reg.isVirtual()) { in getMappedReg() 408 Reg = SI->second; in getMappedReg() 410 if (Reg.isPhysical()) in getMappedReg() 411 return Reg; in getMappedReg() 639 Register Reg = DstReg; in scanUses() local 658 Reg = NewReg; in scanUses() 718 Register Reg) { in rescheduleMIBelowKill() argument [all …]
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H A D | MachineSink.cpp | 311 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock() 604 Register Reg = MO.getReg(); in isWorthBreakingCriticalEdge() local 605 if (Reg == 0) in isWorthBreakingCriticalEdge() 802 Register Reg = MO.getReg(); in isProfitableToSinkTo() local 803 if (Reg == 0) in isProfitableToSinkTo() 901 Register Reg = MO.getReg(); in FindSuccToSinkTo() local 902 if (Reg == 0) continue; in FindSuccToSinkTo() 1333 Register Reg = MO.getReg(); in SinkInstruction() local 1334 if (Reg == 0 || !Register::isPhysicalRegister(Reg)) in SinkInstruction() 1666 if (!Reg) in hasRegisterDependency() [all …]
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H A D | DeadMachineInstructionElim.cpp | 82 Register Reg = MO.getReg(); in isDead() local 83 if (Register::isPhysicalRegister(Reg)) { in isDead() 85 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) in isDead() 92 for (auto &U : MRI->use_nodbg_operands(Reg)) in isDead() 97 for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) { in isDead() 162 Register Reg = MO.getReg(); in eliminateDeadMI() local 163 if (Register::isPhysicalRegister(Reg)) { in eliminateDeadMI() 167 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true); in eliminateDeadMI() 181 Register Reg = MO.getReg(); in eliminateDeadMI() local 182 if (Register::isPhysicalRegister(Reg)) { in eliminateDeadMI() [all …]
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H A D | MachineLICM.cpp | 450 Register Reg = MO.getReg(); in ProcessMI() local 451 if (!Reg) in ProcessMI() 457 if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg))) in ProcessMI() 480 Def = Reg; in ProcessMI() 553 if (!Reg) in HoistRegionPostRA() 599 if (!BB->isLiveIn(Reg)) in AddToLiveIns() 600 BB->addLiveIn(Reg); in AddToLiveIns() 604 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg())) in AddToLiveIns() 834 Register Reg = MO.getReg(); in calcRegisterCost() local 1050 if (MOReg != Reg) in HasHighOperandLatency() [all …]
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H A D | MachineVerifier.cpp | 124 RV.push_back(Reg); in addRegWithSubRegs() 125 if (Reg.isPhysical()) in addRegWithSubRegs() 162 if (!Reg.isVirtual()) in addRequired() 187 return regsLiveOut.count(Reg) || vregsPassed.count(Reg); in isLiveOut() 195 return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id()); in isReserved() 199 return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) && in isAllocatable() 1848 if (!Reg) in visitMachineOperand() 2180 if (Reg.isPhysical() && !isReserved(Reg)) { in checkLiveness() 2402 Dense.insert(Reg); in filterAndAdd() 2775 if (Reg != 0) { in verifyLiveRangeValue() [all …]
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H A D | InlineSpiller.cpp | 219 bool isRegToSpill(Register Reg) { return is_contained(RegsToSpill, Reg); } in isRegToSpill() argument 310 if (isFullCopyOf(MI, Reg)) in isSnippet() 336 RegsToSpill.assign(1, Reg); in collectRegsToSpill() 341 if (Original == Reg) in collectRegsToSpill() 363 return Reg.isVirtual() && VRM.getOriginal(Reg) == Original; in isSibling() 455 Register Reg = LI->reg(); in eliminateRedundantSpills() local 460 if (isRegToSpill(Reg)) in eliminateRedundantSpills() 735 (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) && in reMaterializeAll() 908 if (!Reg || Register::isVirtualRegister(Reg) || MRI.isReserved(Reg)) { in foldMemoryOperand() 1156 spillAroundUses(Reg); in spillAll() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 930 if (!RD.Reg.isVirtual() || !RS.Reg.isVirtual()) in isTransparentCopy() 1690 Changed = HBS::replaceReg(RD.Reg, RS.Reg, MRI); in propagateRegCopy() 1822 Register Reg = RC[I].RefI.Reg; in matchHalf() local 1842 if (RV.RefI.Reg != Reg) in matchHalf() 1874 RH.Reg = Reg; in matchHalf() 2455 if (TopV.RefI.Reg == RD.Reg || TopV.RefI.Pos == W-1) in simplifyExtractLow() 3065 if (V2.RefI.Reg == 0 || V2.RefI.Reg == OutR2) in isSameShuffle() 3253 return G.Out.Reg == P.LR.Reg; in processLoop() 3275 if (!isShuffleOf(G.Out.Reg, G.Inp.Reg)) in processLoop() 3278 return G.Out.Reg == P.LR.Reg; in processLoop() [all …]
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H A D | BitTracker.h | 51 bool has(unsigned Reg) const; 65 void visitUsesOf(Register Reg); 131 return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos); 134 Register Reg; member 146 Register Reg; member 196 BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {} in BitValue() 274 if (V.RefI.Reg != 0) in ref() 275 return BitValue(V.RefI.Reg, V.RefI.Pos); in ref() 281 return BitValue(Self.Reg, Self.Pos); in self() 353 return Map.find(Reg) != Map.end(); in has() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 80 unsigned Reg = CS.getReg(); in assignCalleeSavedSpillSlots() local 84 LowGPR = Reg; in assignCalleeSavedSpillSlots() 120 unsigned Reg = CS.getReg(); in assignCalleeSavedSpillSlots() local 174 unsigned Reg = CSRegs[I]; in determineCalleeSaves() local 175 if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) { in determineCalleeSaves() 243 unsigned Reg = CSI[I].getReg(); in spillCalleeSavedRegisters() local 245 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters() 250 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters() 273 unsigned Reg = CSI[I].getReg(); in restoreCalleeSavedRegisters() local 306 if (Reg != RestoreGPRs.LowGPR && Reg != RestoreGPRs.HighGPR && in restoreCalleeSavedRegisters() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86CallingConv.cpp | 40 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs() local 41 if (!State.isAllocated(Reg)) in CC_X86_32_RegCall_Assign2Regs() 42 AvailableRegs.push_back(Reg); in CC_X86_32_RegCall_Assign2Regs() 53 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs() local 101 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister() local 103 if (!State.isAllocated(Reg)) { in CC_X86_VectorCallAssignRegister() 104 unsigned AssigedReg = State.AllocateReg(Reg); in CC_X86_VectorCallAssignRegister() 111 if (Is64bit && State.IsShadowAllocatedReg(Reg)) { in CC_X86_VectorCallAssignRegister() 167 if (TRI->regsOverlap(Reg, X86::XMM4) || in CC_X86_64_VectorCall() 168 TRI->regsOverlap(Reg, X86::XMM5)) in CC_X86_64_VectorCall() [all …]
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H A D | X86AsmPrinter.cpp | 260 Reg = getX86SubSuperRegister(Reg, Size); in PrintModifiedOperand() 421 Reg = getX86SubSuperRegister(Reg, 8); in printAsmMRegister() 424 Reg = getX86SubSuperRegister(Reg, 8, true); in printAsmMRegister() 427 Reg = getX86SubSuperRegister(Reg, 16); in printAsmMRegister() 430 Reg = getX86SubSuperRegister(Reg, 32); in printAsmMRegister() 438 Reg = getX86SubSuperRegister(Reg, P.getSubtarget().is64Bit() ? 64 : 32); in printAsmMRegister() 456 Index = Reg - X86::XMM0; in printAsmVRegister() 458 Index = Reg - X86::YMM0; in printAsmVRegister() 460 Index = Reg - X86::ZMM0; in printAsmVRegister() 468 Reg = X86::XMM0 + Index; in printAsmVRegister() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst() 106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst() 130 unsigned Reg, int Offset) { in InsertSPImmInst() argument 140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst() 153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst() 175 ScratchBase = Reg; in InsertSPConstInst() 183 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertSPConstInst() 299 Register Reg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 304 InsertFPImmInst(II, TII, Reg, FrameReg, Offset); in eliminateFrameIndex() 309 InsertSPImmInst(II, TII, Reg, Offset); in eliminateFrameIndex() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/ |
H A D | Target.cpp | 451 .addReg(Reg) in loadImmediate() 480 .addReg(Reg) in loadToReg() 535 add(loadToReg(Reg, Opcode)); in loadAndFinalize() 549 if (Reg != X86::ST0) in loadX87STAndFinalize() 558 .addReg(Reg) in loadX87FPAndFinalize() 856 if (X86::GR8RegClass.contains(Reg)) in setRegTo() 858 if (X86::GR16RegClass.contains(Reg)) in setRegTo() 886 if (X86::RFP32RegClass.contains(Reg) || X86::RFP64RegClass.contains(Reg) || in setRegTo() 890 if (Reg == X86::EFLAGS) in setRegTo() 892 if (Reg == X86::MXCSR) in setRegTo() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 100 bool isCallViaRegister(MachineInstr &MI, unsigned &Reg, 112 void incCntAndSetReg(ValueType Entry, unsigned Reg); 172 if (MO.isReg() && MO.getReg() == Reg) { in eraseGPOpnd() 233 unsigned Reg; in visitNode() local 237 if (!isCallViaRegister(*I, Reg, Entry)) in visitNode() 257 incCntAndSetReg(Entry, Reg); in visitNode() 277 Reg = MO->getReg(); in isCallViaRegister() 280 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() 307 unsigned Reg = ScopedHT.lookup(Entry).second; in getReg() local 308 assert(Reg); in getReg() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCTargetDesc.h | 61 unsigned getFirstReg(unsigned Reg); 64 inline unsigned getRegAsGR64(unsigned Reg) { in getRegAsGR64() argument 65 return GR64Regs[getFirstReg(Reg)]; in getRegAsGR64() 69 inline unsigned getRegAsGR32(unsigned Reg) { in getRegAsGR32() argument 70 return GR32Regs[getFirstReg(Reg)]; in getRegAsGR32() 74 inline unsigned getRegAsGRH32(unsigned Reg) { in getRegAsGRH32() argument 75 return GRH32Regs[getFirstReg(Reg)]; in getRegAsGRH32() 79 inline unsigned getRegAsVR128(unsigned Reg) { in getRegAsVR128() argument 80 return VR128Regs[getFirstReg(Reg)]; in getRegAsVR128()
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 278 return UsedRegs[Reg / 32] & (1 << (Reg & 31)); in isAllocated() 345 MarkUnallocated(Reg); in DeallocateReg() 352 if (isAllocated(Reg)) in AllocateReg() 354 MarkAllocated(Reg); in AllocateReg() 355 return Reg; in AllocateReg() 362 MarkAllocated(Reg); in AllocateReg() 364 return Reg; in AllocateReg() 377 MarkAllocated(Reg); in AllocateReg() 378 return Reg; in AllocateReg() 418 MarkAllocated(Reg); in AllocateReg() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | GCNNSAReassign.cpp | 127 unsigned Reg = StartReg + N; in canAssign() local 128 if (!MRI->isAllocatable(Reg)) in canAssign() 148 for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) { in scavengeRegs() local 149 if (!canAssign(Reg, NumRegs)) in scavengeRegs() 152 if (tryAssignRegisters(Intervals, Reg)) in scavengeRegs() 172 Register Reg = Op.getReg(); in CheckNSA() local 173 if (Reg.isPhysical() || !VRM->isAssignedReg(Reg)) in CheckNSA() 176 Register PhysReg = VRM->getPhys(Reg); in CheckNSA() 198 if (VRM->getPreSplitReg(Reg)) in CheckNSA() 214 if (!LIS->hasInterval(Reg)) in CheckNSA() [all …]
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H A D | SIFormMemoryClauses.cpp | 164 Register Reg = MO.getReg(); in canBundle() local 175 if (Reg.isPhysical()) in canBundle() 223 Register Reg = MO.getReg(); in collectRegUses() local 224 if (!Reg) in collectRegUses() 232 auto Loc = Map.find(Reg); in collectRegUses() 348 Register Reg = R.first; in runOnMachineFunction() local 349 if (Reg.isPhysical()) in runOnMachineFunction() 405 Register Reg = R.first; in runOnMachineFunction() local 406 Uses.erase(Reg); in runOnMachineFunction() 407 if (Reg.isPhysical()) in runOnMachineFunction() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVMCInstLower.cpp | 174 unsigned Reg = MO.getReg(); in lowerRISCVVMachineInstrToMCInst() local 176 if (RISCV::VRM2RegClass.contains(Reg) || in lowerRISCVVMachineInstrToMCInst() 177 RISCV::VRM4RegClass.contains(Reg) || in lowerRISCVVMachineInstrToMCInst() 178 RISCV::VRM8RegClass.contains(Reg)) { in lowerRISCVVMachineInstrToMCInst() 179 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); in lowerRISCVVMachineInstrToMCInst() 180 assert(Reg && "Subregister does not exist"); in lowerRISCVVMachineInstrToMCInst() 181 } else if (RISCV::FPR16RegClass.contains(Reg)) { in lowerRISCVVMachineInstrToMCInst() 182 Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); in lowerRISCVVMachineInstrToMCInst() 183 assert(Reg && "Subregister does not exist"); in lowerRISCVVMachineInstrToMCInst() 185 Reg = TRI->getSubReg(Reg, RISCV::sub_32); in lowerRISCVVMachineInstrToMCInst() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kCollapseMOVEMPass.cpp | 209 if (State.isStore() == IsStore && State.getBase() == Reg && in ProcessMI() 218 return ProcessMI(MBB, MI, State, Mask, Offset, Reg, IsStore); in ProcessMI() 221 } else if (Reg == TRI->getStackRegister() || in ProcessMI() 222 Reg == TRI->getBaseRegister() || in ProcessMI() 223 Reg == TRI->getFrameRegister(*MBB.getParent())) { in ProcessMI() 225 State.setBase(Reg); in ProcessMI() 245 unsigned Reg = 0; in runOnMachineFunction() local 263 Reg = MI->getOperand(0).getReg(); in runOnMachineFunction() 269 Reg = MI->getOperand(1).getReg(); in runOnMachineFunction() 275 Reg = MI->getOperand(1).getReg(); in runOnMachineFunction() [all …]
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H A D | M68kRegisterInfo.cpp | 75 M68kRegisterInfo::getMatchingMegaReg(unsigned Reg, in getMatchingMegaReg() argument 77 for (MCSuperRegIterator Super(Reg, this); Super.isValid(); ++Super) in getMatchingMegaReg() 105 int M68kRegisterInfo::getRegisterOrder(unsigned Reg, in getRegisterOrder() argument 108 if (regsOverlap(Reg, TRC.getRegister(i))) { in getRegisterOrder() 115 int M68kRegisterInfo::getSpillRegisterOrder(unsigned Reg) const { in getSpillRegisterOrder() 116 int Result = getRegisterOrder(Reg, *getRegClass(M68k::SPILLRegClassID)); in getSpillRegisterOrder() 127 auto setBitVector = [&Reserved, this](unsigned Reg) { in getReservedRegs() argument 131 for (MCSubRegIterator I(Reg, this, /* self */ true); I.isValid(); ++I) { in getReservedRegs() 137 for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) { in getReservedRegs() local 138 if (MF.getSubtarget<M68kSubtarget>().isRegisterReservedByUser(Reg)) in getReservedRegs() [all …]
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