1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
16 
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsSelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
26 #include <string>
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
30 
31 namespace llvm {
32 class StringRef;
33 
34 class MipsTargetMachine;
35 
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37   virtual void anchor();
38 
39   enum MipsArchEnum {
40     MipsDefault,
41     Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
42     Mips64r2, Mips64r6
43   };
44 
45   // Mips architecture version
46   MipsArchEnum MipsArchVersion;
47 
48   // Selected ABI
49   MipsABIInfo ABI;
50 
51   // IsLittle - The target is Little Endian
52   bool IsLittle;
53 
54   // IsSingleFloat - The target only supports single precision float
55   // point operations. This enable the target to use all 32 32-bit
56   // floating point registers instead of only using even ones.
57   bool IsSingleFloat;
58 
59   // IsFPXX - MIPS O32 modeless ABI.
60   bool IsFPXX;
61 
62   // NoABICalls - Disable SVR4-style position-independent code.
63   bool NoABICalls;
64 
65   // IsFP64bit - The target processor has 64-bit floating point registers.
66   bool IsFP64bit;
67 
68   /// Are odd single-precision registers permitted?
69   /// This corresponds to -modd-spreg and -mno-odd-spreg
70   bool UseOddSPReg;
71 
72   // IsNan2008 - IEEE 754-2008 NaN encoding.
73   bool IsNaN2008bit;
74 
75   // IsFP64bit - General-purpose registers are 64 bits wide
76   bool IsGP64bit;
77 
78   // HasVFPU - Processor has a vector floating point unit.
79   bool HasVFPU;
80 
81   // CPU supports cnMIPS (Cavium Networks Octeon CPU).
82   bool HasCnMips;
83 
84   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
85   bool IsLinux;
86 
87   // UseSmallSection - Small section is used.
88   bool UseSmallSection;
89 
90   /// Features related to the presence of specific instructions.
91 
92   // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
93   bool HasMips3_32;
94 
95   // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
96   bool HasMips3_32r2;
97 
98   // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
99   bool HasMips4_32;
100 
101   // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
102   bool HasMips4_32r2;
103 
104   // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
105   bool HasMips5_32r2;
106 
107   // InMips16 -- can process Mips16 instructions
108   bool InMips16Mode;
109 
110   // Mips16 hard float
111   bool InMips16HardFloat;
112 
113   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
114   bool PreviousInMips16Mode;
115 
116   // InMicroMips -- can process MicroMips instructions
117   bool InMicroMipsMode;
118 
119   // HasDSP, HasDSPR2 -- supports DSP ASE.
120   bool HasDSP, HasDSPR2;
121 
122   // Allow mixed Mips16 and Mips32 in one source file
123   bool AllowMixed16_32;
124 
125   // Optimize for space by compiling all functions as Mips 16 unless
126   // it needs floating point. Functions needing floating point are
127   // compiled as Mips32
128   bool Os16;
129 
130   // HasMSA -- supports MSA ASE.
131   bool HasMSA;
132 
133   InstrItineraryData InstrItins;
134 
135   // We can override the determination of whether we are in mips16 mode
136   // as from the command line
137   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
138 
139   const MipsTargetMachine &TM;
140 
141   Triple TargetTriple;
142 
143   const DataLayout DL; // Calculates type size & alignment
144   const MipsSelectionDAGInfo TSInfo;
145   std::unique_ptr<const MipsInstrInfo> InstrInfo;
146   std::unique_ptr<const MipsFrameLowering> FrameLowering;
147   std::unique_ptr<const MipsTargetLowering> TLInfo;
148 
149 public:
150   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
151   bool enablePostMachineScheduler() const override;
152   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
153   CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
154 
155   /// Only O32 and EABI supported right now.
isABI_EABI()156   bool isABI_EABI() const { return ABI.IsEABI(); }
isABI_N64()157   bool isABI_N64() const { return ABI.IsN64(); }
isABI_N32()158   bool isABI_N32() const { return ABI.IsN32(); }
isABI_O32()159   bool isABI_O32() const { return ABI.IsO32(); }
isABI_FPXX()160   bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
getABI()161   const MipsABIInfo &getABI() const { return ABI; }
162 
163   /// This constructor initializes the data members to match that
164   /// of the specified triple.
165   MipsSubtarget(const std::string &TT, const std::string &CPU,
166                 const std::string &FS, bool little,
167                 const MipsTargetMachine &TM);
168 
169   /// ParseSubtargetFeatures - Parses features string setting specified
170   /// subtarget options.  Definition of function is auto generated by tblgen.
171   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
172 
hasMips1()173   bool hasMips1() const { return MipsArchVersion >= Mips1; }
hasMips2()174   bool hasMips2() const { return MipsArchVersion >= Mips2; }
hasMips3()175   bool hasMips3() const { return MipsArchVersion >= Mips3; }
hasMips4()176   bool hasMips4() const { return MipsArchVersion >= Mips4; }
hasMips5()177   bool hasMips5() const { return MipsArchVersion >= Mips5; }
hasMips4_32()178   bool hasMips4_32() const { return HasMips4_32; }
hasMips4_32r2()179   bool hasMips4_32r2() const { return HasMips4_32r2; }
hasMips32()180   bool hasMips32() const {
181     return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
182            MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
183   }
hasMips32r2()184   bool hasMips32r2() const {
185     return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
186            MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
187   }
hasMips32r6()188   bool hasMips32r6() const {
189     return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
190   }
hasMips64()191   bool hasMips64() const { return MipsArchVersion >= Mips64; }
hasMips64r2()192   bool hasMips64r2() const {
193     return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
194   }
hasMips64r6()195   bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
196 
hasCnMips()197   bool hasCnMips() const { return HasCnMips; }
198 
isLittle()199   bool isLittle() const { return IsLittle; }
isABICalls()200   bool isABICalls() const { return !NoABICalls; }
isFPXX()201   bool isFPXX() const { return IsFPXX; }
isFP64bit()202   bool isFP64bit() const { return IsFP64bit; }
useOddSPReg()203   bool useOddSPReg() const { return UseOddSPReg; }
noOddSPReg()204   bool noOddSPReg() const { return !UseOddSPReg; }
isNaN2008()205   bool isNaN2008() const { return IsNaN2008bit; }
isGP64bit()206   bool isGP64bit() const { return IsGP64bit; }
isGP32bit()207   bool isGP32bit() const { return !IsGP64bit; }
getGPRSizeInBytes()208   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
isSingleFloat()209   bool isSingleFloat() const { return IsSingleFloat; }
hasVFPU()210   bool hasVFPU() const { return HasVFPU; }
inMips16Mode()211   bool inMips16Mode() const { return InMips16Mode; }
inMips16ModeDefault()212   bool inMips16ModeDefault() const {
213     return InMips16Mode;
214   }
215   // Hard float for mips16 means essentially to compile as soft float
216   // but to use a runtime library for soft float that is written with
217   // native mips32 floating point instructions (those runtime routines
218   // run in mips32 hard float mode).
inMips16HardFloat()219   bool inMips16HardFloat() const {
220     return inMips16Mode() && InMips16HardFloat;
221   }
inMicroMipsMode()222   bool inMicroMipsMode() const { return InMicroMipsMode; }
hasDSP()223   bool hasDSP() const { return HasDSP; }
hasDSPR2()224   bool hasDSPR2() const { return HasDSPR2; }
hasMSA()225   bool hasMSA() const { return HasMSA; }
useSmallSection()226   bool useSmallSection() const { return UseSmallSection; }
227 
hasStandardEncoding()228   bool hasStandardEncoding() const { return !inMips16Mode(); }
229 
230   bool abiUsesSoftFloat() const;
231 
enableLongBranchPass()232   bool enableLongBranchPass() const {
233     return hasStandardEncoding() || allowMixed16_32();
234   }
235 
236   /// Features related to the presence of specific instructions.
hasExtractInsert()237   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
hasMTHC1()238   bool hasMTHC1() const { return hasMips32r2(); }
239 
allowMixed16_32()240   bool allowMixed16_32() const { return inMips16ModeDefault() |
241                                         AllowMixed16_32;}
242 
os16()243   bool os16() const { return Os16;};
244 
isTargetNaCl()245   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
246 
247   // for now constant islands are on for the whole compilation unit but we only
248   // really use them if in addition we are in mips16 mode
249   static bool useConstantIslands();
250 
stackAlignment()251   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
252 
253   // Grab relocation model
254   Reloc::Model getRelocationModel() const;
255 
256   MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
257                                                  const TargetMachine &TM);
258 
259   /// Does the system support unaligned memory access.
260   ///
261   /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
262   /// specify which component of the system provides it. Hardware, software, and
263   /// hybrid implementations are all valid.
systemSupportsUnalignedAccess()264   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
265 
266   // Set helper classes
267   void setHelperClassesMips16();
268   void setHelperClassesMipsSE();
269 
getSelectionDAGInfo()270   const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
271     return &TSInfo;
272   }
getDataLayout()273   const DataLayout *getDataLayout() const override { return &DL; }
getInstrInfo()274   const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
getFrameLowering()275   const TargetFrameLowering *getFrameLowering() const override {
276     return FrameLowering.get();
277   }
getRegisterInfo()278   const MipsRegisterInfo *getRegisterInfo() const override {
279     return &InstrInfo->getRegisterInfo();
280   }
getTargetLowering()281   const MipsTargetLowering *getTargetLowering() const override {
282     return TLInfo.get();
283   }
getInstrItineraryData()284   const InstrItineraryData *getInstrItineraryData() const override {
285     return &InstrItins;
286   }
287 };
288 } // End llvm namespace
289 
290 #endif
291